This paper presents an efficient design of AES algorithm's IP core in FPGA using pipelining technique and optimized methods.

文章基于FPGA采用流水线技术和优化设计，提出了一种更高效的AES算法IP核的设计方法。

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This paper introduces the data encryption standard algorithm briefly, and discusses an IP-CORE design and the FPGA implementation of the algorithm.

该文介绍了数据加密标准算法，讨论了该算法的一种IP核设计及其FPGA实现。

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And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.

对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明，文章提出的优化方案可行、有效，极大地降低了硬件资源占用和功耗。

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And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.

对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明，文章提出的优化方案可行、有效，极大地降低了硬件资源占用和功耗。

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