Under pressure of the increase of chip scale and the decrease of timing to market, verification has become the bottleneck of digital IC design.
在芯片规模指数式上升和要求面市时间快速缩短的双重压力下，验证已成为数字集成电路设计的瓶颈。
Chip verification, especially functional verification has become one of the most difficult and challenging issues in IC design.
芯片验证，尤其是功能验证已成为当前集成电路设计中最困难、最具挑战的课题之一。
In integrated circuit (IC) chips design, the verification is one of the most complex and time-consuming step in the chips design flow.
在集成电路(IC)芯片设计中，验证是芯片设计流程中最复杂、最耗时的环节之一。
With the booming of the scale and complexity of IC design, accompanied by the enormous pressure of time-to-market, the reliability of verification is getting lower and lower.
随着集成电路规模和复杂度的急剧提高，尤其面对面市时间的巨大压力，芯片验证的可靠性越来越低。
With the increase of manufacturing level and design scale, verification has become on of the major bottlenecks of IC design.
随着IC制造水平的提升和设计规模的增大，验证成为了IC设计的主要瓶颈之一。
With the increase of manufacturing level and design scale, verification has become on of the major bottlenecks of IC design.
随着IC制造水平的提升和设计规模的增大，验证成为了IC设计的主要瓶颈之一。
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