Slip correlative taking and delay locked loop are used for the synchronization, taking, locking of PN code.
采用滑动相关捕获和延迟锁定环实现伪码的同步、捕获和跟踪；
In this paper, a low-jitter process-independent DLL(delay locked loop) based on self-biased techniques is presented.
本文给出了一种采用自偏置技术的低抖动延迟锁相环，可应用于高频时钟产生电路。
Based on digital delay-locked loop, the mix signal technique is used to implement the digital delay locked loop with the resource control technique.
以数字延迟锁相环为基础，并采用数模混合技术，实现了带电源控制的数字延迟锁相环。
To this end the current multipath estimation delay locked loop(MEDLL) was investigated and improvements were proposed based on the zero-point fixed principle.
为了消除扩频系统中的多径干扰，文章基于稳态零点不变的原则对多径估计延迟锁相环（MEDLL）进行研究及改进。
In this paper we introduce the developmental phase and experimental equipments of long time delay phase-locked loop and also give the field test results via the satellite "Symphonic".
本文叙述了长延时锁相环的研制情况和实验设备，同时也给出了通过“交响乐”卫星的现场试验结果。
Theoretical and numerical results show that the new scheme has an improved performance and remarkable complexity simplicity as compared with the classical digital delay-locked loop.
理论分析和数值结果表明，该方案较传统的延迟锁定跟踪方案明显降低了实现复杂度，而且性能有所提高。
During the design of delay - locked loop, the frame of the whole circuit is introduced and then the principles and implementation of the basic modules are presented.
在数字延迟锁相环设计中，先整体讲述电路的整体构架的设计，然后详细阐述了基本模块的实现方法与原理。
Unlike previous researches, the nonlinear analysis on the effects of delay-difference module employed in the delay phase-locked loop (DPLL)is particularly presented.
与以往研究不同，针对延迟锁相线性化环路的延迟差分环节，着重分析了其非线性特性对环路性能的影响。
Unlike previous researches, the nonlinear analysis on the effects of delay-difference module employed in the delay phase-locked loop (DPLL)is particularly presented.
与以往研究不同，针对延迟锁相线性化环路的延迟差分环节，着重分析了其非线性特性对环路性能的影响。
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