A new method for layout design based on region constraints was presented to resolve the timing closure problem of physical design in deep sub-micron technology.
针对深亚微米工艺下版图设计中存在的时序收敛问题，提出了一种区域约束的版图设计方法。
In deep sub - micron technology, the mount of the static power catches up with the dynamic power gradually and the standby power is becoming an important factor in low power design.
进入深亚微米工艺后，静态功耗开始和动态功耗相抗衡，已成为低功耗设计一个不可忽视的因素。
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.
随着集成电路工艺制程进入超深亚微米甚至纳米级，集成电路的功耗问题显得日益突出。
As the semiconductor manufacturing process technology into the deep sub-micron or even nanometer, power consumption is becoming increasingly prominent.
随着集成电路工艺制程进入超深亚微米甚至纳米级，集成电路的功耗问题显得日益突出。
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