The rapid progress of semi-conductor technology on deep sub-micro and nanometer scale announces the SOC era of IC design.
深亚微米和纳米级的半导体技术迅速进步，使得集成电路的设计已经进入系统集成芯片时代。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
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