The rapid progress of semi-conductor technology on deep sub-micro and nanometer scale announces the SOC era of IC design.
深亚微米和纳米级的半导体技术迅速进步，使得集成电路的设计已经进入系统集成芯片时代。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
The accurate measurements of local micro-stress and strain in ultra deep sub-micron semiconductor structures usually resort to complicated microstructure analysis, measurement methods.
超深亚微米半导体结构中的局域微应力、应变的精确测量通常必须借助复杂的微结构分析、测量手段。
With the IC scaling down to deep-sub micro generation, due to the degradation of performance, any conventional device structure is not applicable to IC.
集成电路器件的特征尺寸进入深亚微米时代后，由于微细化和性能方面的影响，一些传统的器件结构将不再适用。
With the IC scaling down to deep-sub micro generation, due to the degradation of performance, any conventional device structure is not applicable to IC.
集成电路器件的特征尺寸进入深亚微米时代后，由于微细化和性能方面的影响，一些传统的器件结构将不再适用。
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