This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep submicrometer VLSI circuits.
提出了用来评估深亚微米vlsi电路中rlc互连延时的一种新的解析延时模型。
This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep submicrometer VLSI circuits.
提出了用来评估深亚微米vlsi电路中rlc互连延时的一种新的解析延时模型。
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