The on-chip decimation filter is configured for maximum performance and flexibility.
该器件配置片内抽取滤波器，可获得最高性能和灵活性。
An on-board digital multiplexer allows the user to access data from the various stages of the decimation filter.
用户可以通过片上数字多路复用器访问各级抽取滤波器中的数据。
The digital decimation filter taking the important constituent in the Delta-Sigma Analog-to-Digital converter is realized by the multistage structure.
数字抽取滤波器是它的重要组成部分，通常采用多级结构来实现。
According to the character of FPGA, the FIR digital decimation filter is implemented via using distribution algorithms which are based on the technique of looking up table.
根据FPGA芯片的特点，FIR数字抽取滤波器采用分布式算法来实现，这种方法实现的基础是查找表。
By utilizing equivalent transformation and polyphase decomposition of the decimation filter, both hardware cost and operating power of each sub-decimation filter were also reduced.
通过利用抽取滤波器的等价变换和多项分解性质，各滤波器级的硬件电路开销和运行功耗都得到了降低。
Under certain conditions, combining the polyphase filtering structure of decimation filter, put forward an optimum design method of quadrature demodulation receiver, which owns decimation structure.
结合抽取滤波器的多项滤波结构，在一定条件下，推导出了一种含抽取正交解调接收机最优结构设计方法。
CIC filter has proven to be a very effective cell in high-speed decimation and interpolation systems.
CIC滤波器已经被证明是在高速抽取和插值系统中非常有效的单元。
In this paper, the high decimation ratio of digital down converter is studied and the multi-stage decimation algorithm is especially analyzed based on CIC filter, CFIR filter and RRC filter.
研究了高倍抽取的数字下变频设计，重点分析了基于级联积分梳状滤波器、级联补偿滤波器、级联根升余弦滤波器的多级抽样频率算法。
A programmable decimation and interpolation ratio module onnected with multistage cascade integrator comb (CIC) filter is designed to implement high efficient decimator and interpolator.
将可编程抽取、插值器与多级积分梳状滤波器（CIC）相配合，实现高效数字抽取和插值模块。
This paper studies high decimation ratio of digital downconverter given narrow-band signal, and especially analyze mul? stage decimation algorithm based on CIC filter and HB filter.
本文研究了窄带信号条件下，高倍抽取的数字下变频设计，重点分析了基于CIC滤波器和HB滤波器的多级抽取算法。
The user has complete control over the filter response, the filter coefficients and the decimation ratio.
用户对滤波器响应、滤波器系数和抽取率拥有完全的控制权。
In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
In addition, the device offers programmable decimation rates, and the digital FIR filter can be adjusted if the default characteristics are not appropriate for the application.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
In addition, the device offers programmable decimation rates, and the digital FIR filter can be adjusted if the default characteristics are not appropriate for the application.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
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