Secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc.
详细叙述了通讯板接口模块的硬件结构设计，其中，对数据缓冲电路、数据传输速率选择电路、逻辑控制电路等各关键点做了重点介绍；
The A/D decoding circuit received simulation signal form measurement port and converted the signals into data signals which displayed by 7-segment, then signals were sent to data latch.
译码电路接收测量端模拟信号，转化为7段显示的数字信号，发送到数据锁存器上。
Some data sheets contain electrostatic discharge or latch-up TEST results and the associated JEDEC TEST conditions.
有的数据手册还包括静电或闩锁测试结果以及对应的JEDEC测试条件。
A method and apparatus for determining the integrity of data stored in a PROM device provides at least one holding latch connected to two sets of blocks.
一种用于确定存储在PROM中数据的完整性的方法和设备，其中PROM配置了至少一个连接到两组块的保持锁存器。
The buffer velocity is fell by using PingPong latch which combine data into 32 bits being easy to connect with DSP.
利用乒乓锁存降低了对缓存速度的要求并将数据合并成32位，易于与DSP数据传输。
The dynamic latch is adapted to generate an amplified output data signal based at least in part on the input data signal.
所述动态锁存器适于至少部分基于输入数据信号产生放大的输出数据信号。
In some embodiments, a receiver latch circuit, includes a dynamic latch having at least one input terminal to receive an input data signal and at least one latch terminal.
在一些实施例中，接收机锁存器电路包括动态锁存器，该动态锁存器具有至少一个用于接收输入数据信号的输入端子和至少一个锁存器端子。
The dynamic latch includes at least one capacitor, coupled between the at least one input terminal and the at least one latch terminal, to reduce intersymbol interference in the input data signal.
所述动态锁存器包括至少一个耦合在所述至少一个输入端子和所述至少一个锁存器端子之间的电容器，以减少所述输入数据信号中的码间干扰。
The latch circuit may be configured to latch an output data signal generated at the output node.
锁存电路可被配置为锁存在输出节点处生成的输出数据信号。
A comparator circuit based on current-mode control used in PWM controller is presented that is able to compare 3-data at a time and latch output signals.
文中提出了一种用于PWM控制器的比较器输出电路的设计，该电路基于电流模式控制，能够同时对三路输入信号进行比较输出并对输出信号进行锁存。
A comparator circuit based on current-mode control used in PWM controller is presented that is able to compare 3-data at a time and latch output signals.
文中提出了一种用于PWM控制器的比较器输出电路的设计，该电路基于电流模式控制，能够同时对三路输入信号进行比较输出并对输出信号进行锁存。
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