SCSI-1 defined an 8-bit parallel interface with a 5MHz data clock, providing a maximum data transfer rate of 5 megabytes per second (MB/s).
SCSI-1定义了一种具有5MHz数据时钟的8-bit并行接口，能提供最高 5 兆字节每秒（5MB/s）的数据传输速率。
A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided.
它提供一个数据时钟输出(DCO)用于在输出端捕获数据，以及一个帧时钟输出(FCO)用于发送新输出字节信号。
AGI could, its advocates say, work for us around the clock, and drawing on all available data, could suggest solutions to many problems.
那些拥护通用人工智能的人说，它可以全天候为我们工作，利用所有可用的数据，为许多问题提出解决方案。
A real-time clock circuit(X1228)is applied to be an hourmeter, data memorizer and alarm in speedometer.
实时时钟电路（X1228）被用作里程表，数据存储器和车速表中的警报。
In addition to a typically recorded transaction, many innocuous objects, such as parking lots, buildings, and street corners, are instrumented and record large volumes of data around the clock.
除了通常记录的交易之外，许多不活动的事物也被全天不间断地记录下来，比如停车场、建筑物和街道角落，这样数据量就会变得非常大。
Their molecular clock data suggest a much earlier speciation, perhaps prompted by the breakup of the ancient supercontinent of Gondwana around 120 million years ago.
他们的分子钟数据证实更早的时候就出现了物种分化，可能是1亿2千万年前冈瓦纳古陆的破裂引发的。
Geneticists speak of the “molecular clock” that recordsthe passage of time. These molecular data also show how variousorganisms are transitional within evolution.
遗传学家所说的“分子钟（molecular clock）”记录了这一进程，这些分子数据也说明了进化中各物种的过渡关系。
Depending on how the researchers calibrated their clock, the data point to an origin of domesticated rice around 8, 200 years ago.
通过科研人员校对“分子钟”，数据显示出该驯化水稻在大约8200年前的原始稻种。
It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.
这就是移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器会移动一位。
In this case, MCL is the memory clock signal, while MDA is the memory data signal.
在这种情况下，内侧副韧带是内存时钟信号，而MDA是内存数据信号。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse.
在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。
You have a pre-defined variable named total_time for the wall-clock time of the whole data collection.
有一个预定义的变量 total_time，它代表整个数据收集过程的时钟时间。
This makes possible to control the plural flows of data even with the considerable increase for clock frequency.
这使得能够控制复数流动的数据，甚至与相当的增加时钟频率。
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟信号进行控制，从而为器件与微处理器或DSP轻松接口创造了条件。
Sending data from slave to master may use the opposite clock edge as master to slave.
数据从主机发给从机可能会使用与从机发给主机相反的时钟沿。
The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.
预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。
In the cases where there is data with data type TIME that doesn't fit into the 24-hour clock, normalize the data to be compatible with the DB2 data type in MySQL before migration.
对于那些不符合24小时格式数据类型TIME的数据，我们需要在迁移之前将它们规范化为MySQL中兼容db2的数据类型。
And, the system can realize functions of automatic irrigation, drainage warning, real time clock, historical data inquiry, data up-transmission and two-way communication.
系统能够实现自动化灌溉，具有排水警示、实时时钟、历史数据查询、数据上传及双向通信等功能。
Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device.
一些设备有两个时钟，一个用于“捕获”或者“显示”数据，另一个则用于提供将数据输入器件的时序。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
The host changes the data line only when the Clock line is low, and data is read by the device when Clock is high.
只有当时钟线为低的时候，主机才可以改变数据线(也就是将数据写入到数据线)。数据将在时钟为高电平的时候被设备读龋。
In binary synchronous communication, the use of clock pulses to control synchronization of data and control characters.
在二进制位同步通信中，使用时钟脉冲来控制数据和控制字符的同步。
It emphasized the programming thoughts of data collection, display, storage, clock control and RS485 communication in software design.
着重阐述了软件设计中数据采集、显示、存储、时钟控制、RS485通信的编程思路。
In order to accomplish the data process and conversion, the clock generation circuit, 100% modulation signal and 10% signal demodulation circuit are designed.
为了完成数据的处理和交换，分别设计了时钟产生电路、100%调制信号和10%调制信号的解调电路。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis.
使用时钟作为资料在定时关闭已经创造各式各样的问题，特别在逻辑和物理综合。
With time series simulation software, the CPU's I/O ports simulate I2C bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices.
采用软件模拟时序使CPU的I/O口模拟I2C总线，实现了单片机与时钟芯片、温湿度传感器、存储芯片等器件的数据交换。
With time series simulation software, the CPU's I/O ports simulate I2C bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices.
采用软件模拟时序使CPU的I/O口模拟I2C总线，实现了单片机与时钟芯片、温湿度传感器、存储芯片等器件的数据交换。
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