Some new low-noise edge triggered flip-flops are presented, and their logic levels are realized in the current domain by steering a constant dc bias current.
提出以电流信号表示逻辑值的新型低噪声触发器设计，用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。
Some new low-noise edge triggered flip-flops are presented, and their logic levels are realized in the current domain by steering a constant dc bias current.
提出以电流信号表示逻辑值的新型低噪声触发器设计，用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。
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