The improved lifting scheme is adopted to reduce the critical path delay.
采用改进的提升算法，减少了关键路径上的延时。
The carry skip adder optimal block sizes can minimize critical path delay.
优化方块分配的进位跳跃加法器可以缩短关键路径的延时。
Because of the decreased critical path delay, the conversion can be implemented in a single cycle.
关键路径延时的减小，使这一转换可以在单周期内完成。
It's critical path delay is very little, and it operates in the fully-pipelined continuous decoding manner.
它关键路径延时很小，并且为全流水线连续解码工作方式。
Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise.
过程变化的知识对于最优化电路延时，减少时钟倾斜和降低串扰噪声很重要。
Through the synthesis of MAC circuit, it validates that the ideas and methods presented in the paper do well to reduce the critical path delay and circuit gates.
电路综合实验表明采用本文所提出思想和方法可以有效减少MAC关键路径时延和电路门数。
The ‘Task Resource Float’ is the amount of delay that can be applied to a task, performed by a Resource, without introducing a delay into another Critical Path task, performed by the same Resource.
任务资源浮动是指用到同一资源时，在不会另一个关键路径任务延迟的情况下，一个任务可以被延迟的时间。
As the number of taps of filter increases, the structure can be easily extended without increasing the delay of critical path.
随着抽头数量的增长，此结构很容易扩展，且不会增加关键路径的延时。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The 'task Resource Float' is the amount of delay that can be applied to a task, performed by a Resource, without introducing a delay into another Critical Path task, performed by the same Resource.
任务资源浮动是指用到同一资源时，在不会另一个关键路径任务延迟的情况下，一个任务可以被延迟的时间。
In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.
文章在静态时序分析的基础上，提出了一种利用关键路径时延信息提高FPGA分割效率的方法。
In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.
文章在静态时序分析的基础上，提出了一种利用关键路径时延信息提高FPGA分割效率的方法。
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