The hardness of this approach depends mostly on the CPU interrupt structure and context-switch hardware support.
这种方法的硬度主要取决于CPU中断结构和环境转换的硬件支持。
The difference in environments is that this one had the interrupt processing for each Ethernet adapter bound to a CPU on the node in which the adapter resides.
这两个环境之间的差异是，这个环境将每个以太网适配器的中断处理绑定到适配器所在的节点上的一个CPU。
The interrupt controller hardware sends interrupts to any CPU.
中断控制器硬件可以将中断发送到任何CPU。
Each processor on the CPU has its own CSA (current save area) pointer that points to the MST that is to be used when a thread or interrupt handler is interrupted or swapped due to context switch.
CPU上的每个处理器都拥有自己的CSA(当前保存区)指针，指向当线程或中断处理程序由于上下文切换而被中断或交换时使用的MST。
To bind an interrupt to a CPU or group of CPUs, first determine which CPUs should process the interrupt and lay out the bitmask accordingly.
为了将一个中断绑定到某个或某组cpu，首先要决定应该让哪些CPU处理这个中断，然后相应地编写位掩码。
All CPU and interrupt behavior information was also derived from the SAR data.
所有CPU和中断信息也来自sar数据。
The essential hardwares of computer contain CPU, memory, interrupt controller, DMA controller, etc.
计算机硬件的核心器件有CPU、内存、中断控制器、DMA控制器，等等。
A reserved area of memory where the CPU automatically saves the program counter and the contents of working registers when a program interrupt occurs.
内存中的一块留用存储区，当程序中断产生时，CPU自动在其中保存程序计数器和工作寄存器的内容。
Tasklets are scheduled through the softirq mechanism, sometimes through ksoftirqd (a per-CPU kernel thread), when the machine is under heavy soft-interrupt load.
通过软中断机制来调度微线程，当机器处于严重软件中断负荷之下时， 可通过ksoftirqd（一种每CPU内核线程）软中断来调度。
The difference in environments is that this one had the interrupt processing for each Ethernet adapter bound to a CPU on the node in which the adapter resides.
这两个环境之间的差异是，这个环境将每个以太网适配器的中断处理绑定到适配器所在的节点上的一个CPU。
Introducing about CPU abnormal interrupt several normal phenomena, and analyzing an example for interrupt trouble shooting.
简要介绍CPU非正常中断的几种情况，并着重分析一例中断排除的全过程。
Basically, a feature of the CPU that permits the machine to mask an interrupt request until the following instruction has been completed.
中央处理机的一种基本特性，在下一条指令执行完毕前允许屏蔽中断请求。
The analysis and experiments shows that an interrupt must take place during the halt acknowledge cycle of the CPU.
分析与实验结果表明，中断必须发生在CPU的暂停响应阶段。
These devices interrupt the CPU and make it process their requests immediately.
这些设备中断CPU，使CPU立即处理它们的请求。
However, in common embedded system, the real-time clock interrupt will wake up the CPU rapidly and periodically even there is no other devices' interrupt. That will increase system power consumption.
但在一般的嵌入式系统中，当系统进入IDLE状态后，即使没有其他设备中断，实时时钟中断也会不断唤醒CPU，这样就会大大增加系统的功耗。
An interrupt is a signal to the operating system that an event has occurred, and it results in changes in the sequence of instructions executed by the CPU.
中断是通知操作系统某件事件发生的信号，它会改变CPU当前执行的指令顺序。
ST16C554 works in FIFO mode, receives and transmits data by (interrupt) mode with a 16 byte hardware transmit buffer, that will also greatly cut down the load on the CPU.
ST16C 554工作在FIFO模式，采用中断方式收发数据，并有16字节的硬件接收发送缓冲区，降低了CPU的开销。
ST16C554 works in FIFO mode, receives and transmits data by (interrupt) mode with a 16 byte hardware transmit buffer, that will also greatly cut down the load on the CPU.
ST16C 554工作在FIFO模式，采用中断方式收发数据，并有16字节的硬件接收发送缓冲区，降低了CPU的开销。
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