This paper introduces the method of designing LCD controller with CPLD chip.
介绍了一种使用CPLD芯片设计LCD控制器的方法。
Then a way of generating Walsh sequences with CPLD is presented and the Design is described by VHDL on CPLD chip.
运用该方法产生沃尔什序列具有实现方便和需要的存储单元少等优点。
This paper introduces a real-time spaceborne SAR simulator and the hardware design based on the PCI bus and CPLD chip.
论述了星载合成孔径雷达（SAR）回波信号模拟源的一种实时实现方法和基于PCI总线与CPLD的硬件设计。
The adoption of CPLD chip whose hardware logic can be reprogrammed in system helps to enhance the flexibility of system.
CPLD芯片具有硬件逻辑在系统可编程功能，大大提高了系统设计的灵活性。
The hardware is based on the Samsung's ARM microprocessor. A CPLD chip is used to control the interface of the network and IDE.
网络刻录系统的嵌入式处理器选择了三星的ARM处理器，并使用CPLD芯片来控制网络和IDE等接口。
In addition, in order to improve the system reliability in time counting, we adopt CPLD chip to realize the counting function in the design.
同时采用CPLD芯片来完成计数功能，从而提高了系统计时的可靠性。
Making use of large inner capacity and programmable resource of a CPLD chip, a high speed UART with buffer bas been designed to meet communication requirement.
利用CPLD芯片的大容量、可编程特性，设计了具有缓存功能的高速异步串行通信接口芯片，以满足日益提高的快速串行通信要求。
With this method, a new storage system with 16 hard disk is realized by keeping the present computer hard disk design, adding a CPLD chip and three 74HC16245 gate drivers.
该方法融合现有的计算机硬盘设计方法，不改变硬盘的原有工作模式，只是增加一片逻辑芯片和三个74HC16245驱动器，便可实现16个硬盘的存储方式。
The algorithm of CPLD chip designed in this paper, using two pulse-counting and CPLD hardware delay means to achieve the balance between CPLD resource consumption and function.
本文设计的CPLD芯片的算法，采用两级脉冲计数及CPLD硬件延时方法，以达到CPLD资源占用和功能实现的平衡。
This paper introduces the process of realizing color strip signals on CPLD chip EPM7096LC68-7. It ex - plains the logic function design and basic principle in CPLD emphatically.
介绍了使用CPLD芯片EPM 7096lc68—7实现彩条信号的过程，重点介绍了CPLD内部逻辑功能设计和基本原理。
Realizing all needed function such as encoding, sequence control, display control and so on with only one CPLD chip, it can be used to connect CPU with LCD without any other devices.
用一片CPLD芯片就完成了全部的译码、时序控制、显示控制等功能，这样CPU和LCD之间就可能直接用一个CPLD芯片连接了，无需再加入其它的接口器件。
The scheme can be implemented by using the CPLD chip, and used for the channel coder in a radar digital optic-fiber communication system and improving the features of clock extraction.
用复杂可编程芯片(CPLD)实现，并用于雷达数字光纤通信系统的信道编码，提高了时钟提取的性能。
CPLD technology is employed to integrate digital circuit in CPLD chip, which is of great usage to the miniaturization, stability, noise immunity and on-line modification and upgrade of the system.
硬件电路设计采用了CPLD技术，将一些数字电路环节集成在CPLD芯片中，为系统的小型化、稳定性、抗干扰性、在线修改和升级创造了条件。
If you use the CPLD method of configuring the FPGA, you can store both the FPGA bitstream and the required code in a single NOR flash chip; it's probably the simplest system design.
如果使用CPLD方法配置FPGA，则可在一个NOR闪存芯片中存储fpga比特流和所需的代码；这可能是最简单的系统设计。
The focus of research here is how to exploit the chip of AD9854 based on the CPLD device to generate a specific signal waveform.
研究的重点是如何利用CPLD（复杂可编程逻辑器件）开发AD9854芯片的功能，产生特定的信号波形。
The part of data acquisition in the control system is introduced mainly, which USES high-speed data acquisition chip AD7862 and CPLD (complex programmable logic device) to make the system extended.
数据采集部分采用AD 7862芯片，具有高速的数据采集能力，可编程逻辑CPLD的采用，使得系统具有较强的可扩展性。
The method of using CPLD to realize high speed datatrasmission between DSP chip TMS320C6713 and VMEbus onthe backboard is described.
介绍了采用CPLD实现DSP芯片TMS320C6713和背板VME总线之间高速数据传输的系统设计方法。
All circuits are designed by HDL and can be intergrated in one CPLD or FPGA chip, used in the frame synchronization and timing of digital communications receiver.
全部电路由硬件描述语言实现，可以集成在一片CPLD或FPGA芯片内部，用于数字通信系统接收端的帧同步和定时。
Therefore, the main work of this paper described as followed: On the hardware part, it takes charge of the schematic design of image sensor chip, power, CPLD, DSP, memory, and USB2.0 interface.
本文的主要工作如下：在硬件设计方面：系统中图像传感芯片、电源、CPLD、DSP、系统存储器和USB2.0接口等部分的设计实现。
A distinguishing feature of the system is that it is not based on special video overlap chip that is common in this field, but USES DSP and CPLD to finish overlap functions.
系统主要特点是并非基于通常所采用的专用的视频叠加芯片，而是通过DSP和CPLD来实现视频叠加的功能。
The hardware structure is introduced, emphatically the communication interface circuit. The time sequence logic problem between CAN controller chip SJA1000 and AT91RM9200 is solved using the CPLD.
介绍了新型通信控制器的硬件设计，着重描述了通信接口部分，用复杂可编程逻辑器件CPLD解决了CAN 控制器芯片SJA 1000与AT 91RM 9200之间的时序逻辑问题。
This system made use of CMOS digital camera, high performance CPLD, ARM7 chip and Ethernet chip as its hardware platform.
系统主要利用CMOS摄像机、高性能CPLD、ARM7芯片以及以太网接口芯片作为硬件平台。
Hardware circuit includes key control module, display module, plastic module of input signal, single chip computer control module and CPLD main control module.
其中硬件电路包括键控制模块、显示模块、输入信号整形模块以及单片机和CPLD主控模块。
Data acquisition, data processing, and USB communication can be realized by using CPLD, high speed ADC, DSP and USB chip.
利用高速可编程逻辑芯片CPLD，高速adc,DSP芯片和USB芯片实现数据采集，数据预处理和usb通信。
This paper describes the top-down design method, hardware circuit buildup in detail and gives program for CPLD and single chip computer.
本文详细论述了系统自上而下的设计方法及各部分硬件电路组成及单片机、CPLD的软件编程设计。
This paper introduces a design based on chip microcomputer and CPLD, analyzes its advantage and disadvantage in detail and gives the hardware-software design frame and thought.
本文详细介绍了一种以单片机和可编程逻辑器件为控制核心的设计方案，并分析了该方案的优缺点，同时给出了硬件和软件设计的结构及思路。
In system digital part design, all outer logic circuits of Single chip microcomputer are implemented in CPLD. That makes the volume of the system smaller and improve the reliability of system.
在系统数字部分的设计中，采用CPLD来实现单片机外部的逻辑电路，大大缩小了整个系统的体积提高了系统的可靠性。
This is a complete system whose core is based on single chip AT89C52 and CPLD.
系统以单片机at89 C5 2及可编程逻辑器件为核心，构成完备的测量系统。
This is a complete system whose core is based on single chip AT89C52 and CPLD.
系统以单片机at89 C5 2及可编程逻辑器件为核心，构成完备的测量系统。
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