A plurality of other correction bits 56, 57 and so on implemented in the same way as bit 50 are provided.
以与位50相同的方式而实现的多个其它的校正位56,57等被提供。
It can be seen that, for simplicity, the input voltage is not sampled onto these correction bit capacitors.
可以看到，为了简化，输入电压未被采样到这些校正位电容器上。
Introducing an offset to increase the resolution of the conversion has been described with the specific case of a 12 bit converter with 3 correction bits in mind.
注意用具有3个校正位的12位转换器的特定情况描述了引入偏移以提高转换的分辨率。
The effect of each correction bit trial is to allow the ADC to reduce the DAC error if a large noise event (of either sign) has caused a wrong decision to be made on a previous bit trial.
每个校正位试验的作用是如果(具有任何符号的)大噪声事件已对在前位试验做出了错误的判定，则使得ADC减少DAC误差。
First let me back up a bit and talk about vision correction before the printing press.
让我先回顾下在印刷术之前的视力矫正是什么样的。
For most Web sites, that's worth more than a little bit of tedium and error-correction.
对多数网站而言，和稍微麻烦一点以及错误纠正相比，这些都是值得的。
Finally, you'll discover tricks for getting better green screen keys and how to do a little color correction for the final bit of polish.
最后，你会发现窍门获得更好的绿色屏幕键，以及如何做一个小的颜色修正的最后一点波兰。
The converter has a good tradeoff between conversion speed and conversion precision. It is a 1.5-bit per stage with 9 stage and digital correction technique.
本设计为兼顾模数转换器的速度和精度，采用数字校正技术，以每级1.5 位的9 级流水线结构实现。
They are mixed bit encoding based an sample organization mode, memory queue of weight and transitional point and correction method.
权值和迁跃点记忆队列的网络训练方法和结果校正方法。
Against the bit error when the picture is compressed, with JND model in order to keep invisible, a new bit error correction method is proposed based on extraction-comparison.
针对图像压缩时所导致的误码，利用JND模型，提出了一种新的基于提取对比的误码修正算法。
In this paper we briefly introduce some basic concepts of quantum computing which include quantum entanglement, quantum bit, quantum register, quantum parallel computing and quantum error correction.
本文简要地介绍量子计算的一些基本概念：量子纠缠、量子位、量子寄存器、量子并行计算和量子纠错。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
The test data of bit error rate and signal-to-noise ratio show that the performance of the receiver terminal is available, which guarantees the accuracy of the data after the forward error correction.
从比特误码率、信噪比等测试结果数据分析可知，接收终端的性能合格，经过前向纠错后可以保证用户数据的准确性。
Finally, according to the figures mentioned in this article correction techniques, to build a 10-bit digital correction circuit, through the functional simulation to verify its functionality.
最后根据本文中提到的数字校正技术，搭建一个10位的数字校正电路，通过功能仿真来验证功能。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
应用推荐