These major changes in voltage, core clock and memory clock can easily destabilize a card to a point where you get artifacting and even a lockup.
这些在电压、核心时脉和记忆体时脉的改变，容易造成显卡的不稳甚至当机。
Clock Synchronization is one of core technologies in Distributed Systems and Communication Fields.
时钟同步是分布式系统、通信领域中的核心技术之一。
The magical warmth deep in the core of Narbondel—the natural stone pillar that served as the city's clock—was climbing toward midpoint as the unseen sun reached its zenith.
当幽暗地域中从未见过的太阳到达天顶时，作为城市时钟的天然石柱纳邦德尔，魔法之火产生的热度正沿着石柱的核心攀向中点。
The problem of Clock Synchronization is a classical issue in distributed operating system and core technology in distributed computing.
时钟同步问题是分布式操作系统中的一个经典的问题，是分布式计算中的核心技术之一。
Finally, Intel has plans to quickly transition to multi-core architecture across all of its product lines and most industry watchers expect processor clock speeds to level off in the years ahead.
最后，英特尔计划使其全线产品加快向多核体系结构转换，同时业内分析人士期望处理器时钟速度可以在未来几年内趋于平稳。
STC89C52 microcontroller modules: microcontroller STC89C52 single-chip, reset circuit, clock circuit constitute the core of the whole system.
STC 89c52单片机模块：由单片机STC 89c52单片机、复位电路、时钟电路等构成，是整个系统的核心。
The micro-processor and VLSIC are core of the master clock, which consists of a control unit and can adjust all slave clocks (except standard time slave clock) clockwise and inversion quickly.
器件为核心，构成一控制单元，操作非常简单，且可以同时对所有子钟进行顺时针和逆时针快速调整，运行可靠。
One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a core module of microprocessor.
锁相环在微处理器领域中的一个重要应用就是为系统提供片内时钟，它是微处理器时钟电路中的核心模块。
The chip of AT89C2051 is based on as the core of intellectual electronic-clock, and the scanning mode is applied to display by combining dynamic scan with static scan.
多功能智能电子钟以AT89C2051芯片为核心，采用静态与动态相结合的扫描方式显示。
The bus and the processor core often run in different clock frequencies, so their interface signals belong to different clock domains.
总线时钟与处理器内核时钟频率不同，因此总线部件与处理器内核间的接口信号需要进行时钟域转换。
Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle.
另一个独特的构架特性是内存系统，它允许一个取指，并在同一时间，每一个核可以读取数据在每一个单独的时钟周期内。
The higher the clock frequency is, the more PLL influences the performance of microprocessors. PLL technique has been one of the core techniques in modern microprocessor design.
随着时钟频率的不断提高，微处理器的性能受锁相环的影响越来越大，锁相环技术已经成为当代微处理器的核心技术之一。
While its quad-core "Shanghai" Opterons reached a maximum frequency of 2.3GHz, the six-core part had to give up some clock speed, down to 1.8GHz, to manage the thermal load for six cores.
虽然它的四核心“上海”Opteron处理器达到了2.3GHz的最高频率，六核心部分不得不放弃一些时钟速度，降低到1.8GHz，以管理六核热负荷。
While its quad-core "Shanghai" Opterons reached a maximum frequency of 2.3GHz, the six-core part had to give up some clock speed, down to 1.8GHz, to manage the thermal load for six cores.
虽然它的四核心“上海”Opteron处理器达到了2.3GHz的最高频率，六核心部分不得不放弃一些时钟速度，降低到1.8GHz，以管理六核热负荷。
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