The problem of fault detection in general combinational circuits is a NP-complete problem.
组合电路的故障检测问题是一个NP完全问题。
The test generation algorithm for non-robust path delay fault in combinational circuits is studied.
研究了组合电路中非鲁棒性路径时滞故障的测试生成算法。
This paper presents a method to the problem of optimizing technology mapped combinational circuits for low power.
本文介绍了一种优化经工艺映射的组合逻辑电路功耗的方法。
Practical examples show that this technique is Valuable for the design of combinational circuits to a certain extent.
设计实例表明，该技术对组合电路的设计具有一定的实用价值。
Then, a new method testing the double fault of combinational circuits based upon Boolean partial derivative is proposed.
在此基础上提出了基于布尔偏导数的组合电路双故障检测的新方法。
It can translate the bit level description of the specification of combinational circuits and sequential circuits into word level polynomials.
它能把组合电路和时序电路的位级描述的设计规范表示成字级多项式。
Compared with the method only using universal cut or special cut, the method can obviously improve the speed of verification for combinational circuits.
与只基于通用割集或专用割集的验证方法相比，该方法可以使组合电路的验证速度明显提高。
This paper propose a functional fault for delay faults in combinational circuits and describe a functional test generation procedure based on this model.
提出一种用于测试组合电路中延迟故障的新功能故障模型，讨论该模型的功能测试生成。
On the basis of the multiple-valued switch-level algebra, this paper proposes a logic design automation algorithm for NMOS and CMOS combinational circuits.
本文在多值开关级代数理论的基础上，提出了适合于NMOS及CMOS组合电路的逻辑设计自动化算法。
This paper probes into the principle and method of using blocking method to optimize the design of combinational circuits with restraint conditions and gives examples to illustrate their application.
探讨了在卡诺图中利用阻塞法优化设计具有约束条件组合逻辑电路的原理和方法，并举例说明应用。
According to a requirement of design, the optimum parameters of combinational logic circuits can be obtained after running the program.
根据设计要求，通过本程序的运行，可获得最佳的组合逻辑电路的参数。
This paper proposed a new algorithm of retiming which can be combined well with other combinational optimization methods to speed up logic circuits.
提出了一种改进时序重排算法，使时序重排可以更有效地与其他组合优化算法结合起来，共同提高同步时序电路的速度。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance.
仿真实验结果证明了改进演化算法对于实现函数级数字组合逻辑电路的硬件演化是可行的，并且提高了演化算法的演化效率和收敛性能。
The methods designing TSC and TSC circuits with code disjoint property for any combinational function are given.
本文给出了将任意组合函数设计为全自检线路，以及具有编码分离性质的全自检线路的方法。
The properties of Boolean difference are made use of to derive a new method for fault testing in combinational logic circuits. This method is simpler and different from the traditional one.
本文利用布尔差分的性质，给出了一种不同于传统的求组合逻辑线路故障测试码的新方法，对故障测试有一定的简化作用。
And combinational logic circuits by using VHDL language and in two ways, comparing the merits of the two implementations and different design processes and ideas.
并且通过应用组合逻辑电路和VHDL语言实现两种方法，对照了两种实现方法的优劣及不同的设计流程和思想。
The paper also discusses the design principle of super-high-speed digital circuits and some examples of combinational and sequential circuits using linear AND-OR gate are given.
本文还讨论了应用线性“与或”门设计超高速数字电路的准则以及有关的组合和时序电路设计实例。
To stress the application of Karaugh map on designing of coding circuits in parallel-comparator ADC in terms of the design of combinational logic circuits.
根据组合逻辑电路的设计方法，突出用卡诺图化简逻辑表达式在并联比较型A/D转换器编码电路设计中的应用。
In this paper the writer tries to integrate the design of asynchronos counters of arbitrary carry system with the design of combinational logic circuits in concept and method.
本文试图把时序逻辑电路和组合逻辑电路的设计，在概念上和方法上统一起来。
By comparing with the present parallel circuits, there are some advantages, less coding states and simpler combinational network, in the circuit proposed. Therefore, it is a valuable circuit model.
和目前的并接电路相比较，它具有更少的编码状态和更简的组合网络，因此，这是一种有价值的电路。
But, the Combinational Logic Circuits possible isn't a most simple Combinational Logic Circuits.
但是利用最简逻辑函数实现的逻辑电路却不一定是最简的逻辑电路。
But, the Combinational Logic Circuits possible isn't a most simple Combinational Logic Circuits.
但是利用最简逻辑函数实现的逻辑电路却不一定是最简的逻辑电路。
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