C1E tries to provide more power savings than the traditional C1 state (which only halts the clock signal) by also lowering the voltage and frequency.
同样通过降低电压和频率，C1E尝试比传统C1状态(只会停止时钟信号)提供更大的电能节省。
Low-power oriented design techniques include selecting low-power parts, low operation voltage, managing clock of MCU or making MCU turn into dormancy, managing power supply of circuit and so on.
低功耗设计的关键技术包括选用低功耗的各类器件，低工作电压，对MCU进行时钟管理或休眠，对各部分电路和器件进行电源管理等。
Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accomplished by an external clock signal.
它的功能是当感应到输入电压界限时提供一个锁存开关，通过外部时钟信号完成复位。
Clock timing affects crosstalk because it slightly changes the relative time of arrival of aggressive voltage spikes.
时钟选择影响干扰，因为它仅仅改变电压毛刺到达的相对时间。
The reference capacitor can charge at a third clock phase, thus the input signal is released from the capacitor dependently from the voltage.
参考电容器可以在第三时钟相位放电，这样输入信号依赖电压从电容器被释放。
The clocking circuit configured to provide the pull-up current to an internal node in response to a clock signal having the input supply voltage and the ground voltage.
时钟电路被配置为响应于具有输入供电电压和接地电压的时钟信号向内部节点提供上拉电流。
The invention can implement amplitude-limiting function without affecting the posterior demodulation, voltage stabilization, and normal operation of the clock and the reset circuit.
本发明既能完成限幅功能，又不会影响 芯片内部后续解调、稳压、时钟、复位电路的正常工作。
These major changes in voltage, core clock and memory clock can easily destabilize a card to a point where you get artifacting and even a lockup.
这些在电压、核心时脉和记忆体时脉的改变，容易造成显卡的不稳甚至当机。
The factors which will be encountered are descried and modules include anti-aliasing filter, clock circuit, band gap voltage reference, sc integrator, latched comparator and DAC are designed.
最后在考虑实际因素的基础上，依次设计了时钟产生电路、前置滤波器、带隙基准源、开关电容积分器、锁存比较器和DAC等子模块电路并做了仿真。
The factors which will be encountered are descried and modules include anti-aliasing filter, clock circuit, band gap voltage reference, sc integrator, latched comparator and DAC are designed.
最后在考虑实际因素的基础上，依次设计了时钟产生电路、前置滤波器、带隙基准源、开关电容积分器、锁存比较器和DAC等子模块电路并做了仿真。
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