The device always generates the clock signal.
时钟信号总是由设备端生成的。
A clock signal input is designed to supply a clock signal.
时钟信号输入端被设计用于提供时钟信号。
CLOCK SIGNAL, a continuous string of pulses used for synchronization.
时钟脉冲，用于同步的连续脉冲信号串。
We know that the hardware circuit design clock signal is very important.
我们知道，在硬件电路设计中时钟信号时非常重要的。
In this case, MCL is the memory clock signal, while MDA is the memory data signal.
在这种情况下，内侧副韧带是内存时钟信号，而MDA是内存数据信号。
Clock signal and clock skew become more and more important in the circuit performance.
时钟信号和时钟偏差对电路性能的影响也越来越明显。
Data sent from the device to the host is read on the falling edge of the clock signal;
从设备发送给主机的数据时在时钟信号的下降沿读取的；
We know that the hardware circuit design clock signal is the most important one of the signals.
我们知道，在硬件电路设计中时钟信号是最重要的信号之一。
The embodiment of the invention provides a method for detecting a clock signal and a device thereof.
本发明实施例提供了一种检测时钟信号的方法及装置。
Arbitrary phase clock management devices can produce high-precision dynamic phase of the clock signal.
任意相位时钟管理器可以产生高精度动态相位的时钟信号。
The latest three-phase clock signal control method was used to control the working state of charge pump.
电路采用了预启动和衬底电位选择结构，并利用三相时钟信号方式控制电荷泵的工作状态。
These persistent registers are powered by a battery and receive a timing clock signal from a crystal oscillator.
这些持续不断的寄存器由电池供电，并接收来自晶体振荡器计时的时钟信号。
The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal.
你的微型计算机执行程序的速度将与你的时钟信号的速度成线性关系。
In clock routing, clock signal and clock skew become more and more important for impact of the circuit performance.
在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。
The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.
输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。
This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement.
这样确定并使用时钟信号上升沿的位置作为定时测量。
The paper introduce the circuit on conversing difference signal to TTL , and introduce in detail how to gained bit-clock signal .
本文主要详细讲述了如何利用差分变换后的波形提取位时钟信号。
Additionaly, by using of 16-bit counters and external 2mhz clock signal, the distinguishability of the control Angle is increased.
又因采用外加2m时钟作为计时信号，提高了控制角的分辨率。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
The test circuit receives the second clock signal and the first clock signal outputted by the first IC chip to generate a comparable signal.
检测电路接收第二时钟讯号和第一集成电路芯片所输出的第一时钟讯号，以产生一比较讯号。
The clock signal is obtained by using a frequency doubler which USES a modified XOR topology, so that the complexity of the system is reduced.
改进异或门拓扑结构实现的二倍频器，结构简单、实用，降低了电路复杂度。
C1E tries to provide more power savings than the traditional C1 state (which only halts the clock signal) by also lowering the voltage and frequency.
同样通过降低电压和频率，C1E尝试比传统C1状态(只会停止时钟信号)提供更大的电能节省。
Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accomplished by an external clock signal.
它的功能是当感应到输入电压界限时提供一个锁存开关，通过外部时钟信号完成复位。
The interface circuit also can produce synchronous, vanished and ensconced, digital clock signal and realize remote control, displaying on screen.
同时产生同步、消隐、数据时钟等信号以及实现遥控、屏幕显示的控制功能。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
With the signal from the master clock, the slave clock is able to recover an accurate local clock signal using a Clock Recovery Phase Locked Loop (PLL).
从时钟利用主时钟发来的时钟信号，通过数字锁相环恢复出本地时钟信号。
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟信号进行控制，从而为器件与微处理器或DSP轻松接口创造了条件。
The clocking circuit configured to provide the pull-up current to an internal node in response to a clock signal having the input supply voltage and the ground voltage.
时钟电路被配置为响应于具有输入供电电压和接地电压的时钟信号向内部节点提供上拉电流。
The clocking circuit configured to provide the pull-up current to an internal node in response to a clock signal having the input supply voltage and the ground voltage.
时钟电路被配置为响应于具有输入供电电压和接地电压的时钟信号向内部节点提供上拉电流。
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