The high frequency clock allows for a greater sampling rate, which results in higher accuracy and faster signal processing capability .
高频时钟可支持更高的取样率，从而达到更高的精确度和更快的信号处理能力。
Generally sampling pulse is produced by the control of clock inner device.
一般采样脉冲都是在装置内部时钟的控制下产生的。
The frequency synchronization and sampling clock synchronization technique in high definition TV (HDTV) are investigated.
研究了高清晰度数字电视(HDTV)中的频率同步及采样钟同步技术。
As to phased array receiving, a scheme of separating the delay clock and sampling clock is explicated, which effectively enhance the phased receiving delay resolution.
对于相控接收延时，本文阐述了一种将延时时钟和采样时钟分离的方案，有效地提高了接收延时分辨率。
We describe the synchronization technique in several keys including symbol timing, carrier frequency offset estimation and sampling clock offset estimation.
符号定时同步技术，载波频率同步技术和采样钟同步技术等几个方面。
The CEC technique compensates the sampling bandwidth by eliminating the impact from finite on-resistance of the sampling switch, and avoids increasing clock feedthrough and charge injection.
该技术通过消除采样开关有限导通电阻的影响，补偿了采样带宽，并避免了时钟馈通和电荷注入的加剧。
It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.
它内置一个低功耗、高速、16位不失码的采样adc、一个内部转换时钟和一个多功能串行接口。
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。
The method is a fully-digitized process at the sampling clock rate, so that it can be conveniently implemented by FPGA or DSP, whose synchronization precision can reach 1% of the sampling interval.
该方法是一种基于信号采样时钟速率的全数字化处理过程，其同步精度可达到信号采样间隔的1%以上，且便于FPGA或DSP实现。
Application of the technology of sampling in different phase in clock circuit realizes maximum 200m equivalent sampling rate of timing analyzer.
在时钟电路中采用分相采样技术，实现了定时分析最高200m的等效采样速率。
The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.
差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
The clock signal provided by Global Positioning System(GPS)is widely used in electric power system for relay protection, SOE (Sequence of Events), fault locating, synchronous sampling and so on.
GPS同步时钟信号已在电力系统的继电保护、事件顺序记录、故障测距、同步采样等诸多领域获得重要运用。
Using the clock synchronization, synchronous sampling could be realized on an asynchronous control network.
为了能在异步控制网络上实现采样同步，可采用时钟同步方法。
This thesis selects model GN-80 GPS receiver and SCM to design the sampling device. The high accurate time service is used to synchronize the sample clock signal to realize synchronous sampling.
选用GN-80型GPS接收设备和单片微机进行电力系统状态变量同步采集终端的硬件设计，利用GPS的精确授时作为其同步时钟控制采样脉冲来实现同步采样。
Offering direct digital frequency synthesis (DDFS) based on the frequency -phase to achieve the following sampling clock.
提出基于频相的直接数字频率合成技术（DDFS）实现采样的跟随时钟。
In the digital oscilloscope signal equivalent sampling method, a sampling clock with two inverse ways is utilized for sampling, thereby effectively eliminating the phenomena of uplift and burr.
所述数字示波器信号等效采样方法利用两路相反的采样时钟进行采样，有效的消除了隆起现象和毛刺现象。
This circuit is implemented on a monolithic chip, which is comprised of a period time sampling unit, a peri-od distanee preset unit, an arithmetic unit, a clock and time sequence unit.
电路主要由周期计时电路、周期数据预置电路、运算电路及时钟和时序等电路构成。
The high frequency clock allows for a greater sampling rate, which results in higher accuracy and faster signal processing capability.
高频时钟可支持更高的取样率，从而达到更高的精确度和更快的信号处理能力。
Pixel clock output frequencies range from 10mhz to 140mhz with sampling clock jitter of 250ps peak to peak.
像素时钟输出频率范围从10mhz到140mhz的采样250ps的峰峰值抖动。
The low power consumption digital true random source comprises a high speed random oscillator signal generator, an alternative oscillation stop control unit, a clock generator and a sampling unit.
它包括高速随机振荡信号发生器、交错停振控制单元、时钟发生器和采样单元。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
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