The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.

预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。

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Simulation results show the PLL clock frequency multiplier has lower phase noise and shorter capture time.

结果表明，PLL倍频器具有较低的噪声和较高的捕获速度。

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Simulation results show the PLL clock frequency multiplier has lower phase noise and shorter capture time.

结果表明，PLL倍频器具有较低的噪声和较高的捕获速度。

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