The real time clock module provides is divided into an analog and a digital domain.
实时时钟模块提供的是分为模拟和数字域名。
The hardware includes GPS receiver, pulse peak acquisition card, GPS clock module and industrial computer.
系统硬件部分包括GPS接收机、GPS时钟模块、脉冲峰值采集卡及工控机。
The FLL clock module is designed to meet the requirements of both low system cost and low power consumption.
在FLL时钟模块旨在满足要求的低系统成本和低功率消耗。
Otherwise, the electric level transform of memorizer and the configuration of clock module are analyzed in detail.
并对存储器的电平转换以及时钟模块的配置进行了详细的分析。
A real time clock module maintains operating and timing parameters in "non-volatile" or persistent memory when an integrated circuit is powered down.
实时时钟模块的维护工作和时间“非易失性”，或当一个永久的记忆集成电路关机参数。
The main system chips used EP1K100QC208-3, make up of the clock module, control module, time module, data decoding module, display and broadcast module.
系统主芯片采用EP1K100 QC 208 - 3，由时钟模块、控制模块、计时模块、数据译码模块、显示以及报时模块组成。
And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.
论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。
Firstly it discusses the approach of logical clock and revise algorithm of logical clock, then introduces the implementation approach of logical time monitor module in distributed S4 system.
首先讨论了逻辑时钟方法及逻辑时钟的修改算法，然后介绍了自行研制的分布式s4系统中逻辑时钟监控器模块的实现方法。
SMU module adopts the clock-gating method was applied to the survivor path storage block, reduce the survivor path storage memory power dissipation effectively.
在幸存路径管理模块采用门控时钟的方法，有效地降低了对幸存路径存储部分的功耗。
A new smoothness tester has been designed and accomplished. This paper presents in details the module design of controller, data acquisition, man-machine interface and real clock.
设计了一种新型平滑度仪，详细描述了控制器、数据采集、人机接口和实时时钟等模块的具体选型及设计；
The asynchrony FIFO module can be applied in the other asynchrony interface circuit design in multi-clock system.
异步fifo的设计方案对于多时钟系统中异步接口电路的设计具有一定的参考价值。
Hardware in this system is made up by data acquisition module, data storage module, data transport module, real-time clock, power supply and so on.
系统硬件由数据采集、数据存储、数据传输、实时时钟、电源等模块组成。
The FIFO module in FPGA was applied to realize the pixel clock modification and the data saving and taking.
采用FPGA内部集成的FIFO模块实现像素时钟的改变和图像数据的存取。
One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a core module of microprocessor.
锁相环在微处理器领域中的一个重要应用就是为系统提供片内时钟，它是微处理器时钟电路中的核心模块。
Through the software the practical watching clock for interface module of GPS is implemented and the dependence on the PPS pulse is reduced.
GPS接口板通过软件方式实现实用化的守时钟，降低对单个PPS秒脉冲的依赖性。
Associated logic and clock trees contained in a disabled module will therefore stop consuming power.
被禁用的模块中包含的相关逻辑和时钟树会因此停止消耗能量。
The software design is finished, including system initialization, clock read and write, tracking Control, motor Drive module and so on.
同时完成了系统的软件设计，主要包括系统初始化，时钟读写，跟踪控制，电机驱动等。
The software design is finished, including system initialization, clock read and write, tracking Control, motor Drive module and so on.
同时完成了系统的软件设计，主要包括系统初始化，时钟读写，跟踪控制，电机驱动等。
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