The problem might be an interaction between components or an IC that fails when run at normal operating clock rates.
问题可能出在器件的互连或工作在正常的时钟频率时集成电路就不能正常的运行了。
In deep submicron era, IC design in physical design has more and more challenge, with the increasing design scale, faster clock frequency and minimizing process dimension.
在深亚微米时代，随着设计规模变大，时钟频率越来越高以及工艺尺寸的减小，IC物理设计面临着诸多困难。
The test circuit receives the second clock signal and the first clock signal outputted by the first IC chip to generate a comparable signal.
检测电路接收第二时钟讯号和第一集成电路芯片所输出的第一时钟讯号，以产生一比较讯号。
The test circuit receives the second clock signal and the first clock signal outputted by the first IC chip to generate a comparable signal.
检测电路接收第二时钟讯号和第一集成电路芯片所输出的第一时钟讯号，以产生一比较讯号。
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