Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
When processors operate at a lower clock speed, they consume proportionately less power and generate less heat.
当处理器以较低的时钟速度运行时，它们消耗的电能和产生的热量也相对较少。
Today’s grid cannot generate enough electricity even to power a 40-watt bulb around the clock for every Nigerian—and rarely runs at full capacity.
现在的尼日利亚电网甚至不能为每个国民提供一盏40瓦电灯持续照明的电力——且几乎从不全力运营。
Based on the system clock and trigger input signals, using FPGA to generate trigger output signals in given working modes.
通过FPGA实现在一定系统时钟和触发信号作用下各种工作模式的触发信号的产生。
Through controlling an N-bit accumulator and then get its highest bit to generate the programmable clock.
通过控制一个N位累加器累加，取其最高位，即可得到可编程时钟源。
The direct digital synthesis (DDS) is adopted to generate the pseudo-random code clock having high precision and stability.
利用直接频率合成技术产生高精度、高稳定度的扩频伪码时钟。
ICS1523 is a high performance programmable line-lock clock generator with the I2C serial bus interface. User can use it to generate desired line-locked clock by programming it.
ICS1523是一种高性能可编程行同步信号发生器，它带有一个I2C串行总线接口，可以方便地对内部寄存器进行配置，能产生用户需要的同步信号。
It can reduce the time used to generate the test vectors by using the clock test.
并使用时钟测试来减少生成测试向量所需的时间。
The test circuit receives the second clock signal and the first clock signal outputted by the first IC chip to generate a comparable signal.
检测电路接收第二时钟讯号和第一集成电路芯片所输出的第一时钟讯号，以产生一比较讯号。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
Then we propose an algorithm to generate an optimal PD connection structures resulting in the minimum clock skew.
接著，我们提出一个能够产生最小时脉偏移之相差侦测器架构的演算法。
The circadian clock genes, which generate circadian rhythms and maintain its the running, exist in organisms ranging from prokaryotes to mammals.
生物钟基因普遍存在于生物界，其作用在于产生和控制昼夜节律的运转。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
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