During a WRITE operation, When this command is issued, data inputs can't be written with no clock delay.
在写操作中，如果该指令发出，输入数据马上无法写入。
During a READ operation, When this command is issued, data outputs are disabled and become high impedance after two clock delay.
在读操作中，如果发出了这个指令，那么两个时钟周期后，读出数据无效，数据总线进入高阻状态。
A non-clock delay-ring A/D converter is presented, which is based on standard cell library and not sensitive to process variation.
提出了一种无需外部时钟、可以部分抵消工艺偏差、基于标准单元的延迟环A/D变换器。
The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.
差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。
After analyzing the Clock delay, the Clock Skew and the critical steady synchronizer which are difficult in the design, some settle methods are introduced.
同时就设计中常遇到的三个问题：时钟延时，时钟偏移，同步器的亚稳态性加以说明且提出了解决方法。
The whole design is described in VHDL. By logic optimization, the controller has an advantage of less resource utilization and less clock delay compared with other similar controllers.
整个设计采用VHDL语言描述，经过逻辑优化，该显示控制器有着比同类控制器占用资源少、时钟延迟小等优点。
The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.
预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。
A simple performance metric is wall clock time, or measuring the real-world delay between a request for a page and a finished rendering.
一个简单的性能指标是挂钟时间(wallclock time)，或测量页面请求与完成呈现之间的实际延迟。
After the examples are analyzed, there are problems which need to be solved such as ambiguity, real-time clock bias error and the estimate method of zenith wet delay.
通过对算例的分析，提出需要解决的问题：整周模糊度、实时钟差和天顶湿延迟的估计方法。
This paper adopts a strategy of fitting offset to adjust time, to conquer the impact of network delay and jitter on clock synchronization effectively.
该文提出采用拟合偏差方法进行时钟调整的策略，以有效克服网络延迟和抖动对时钟同步的影响。
As to phased array receiving, a scheme of separating the delay clock and sampling clock is explicated, which effectively enhance the phased receiving delay resolution.
对于相控接收延时，本文阐述了一种将延时时钟和采样时钟分离的方案，有效地提高了接收延时分辨率。
Secondly, controller design of NCS for delay compensation is studied when the controller is clock-driven.
其次，研究了控制器为事件驱动时网络控制系统的时延补偿控制。
The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。
Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise.
过程变化的知识对于最优化电路延时，减少时钟倾斜和降低串扰噪声很重要。
And the clock synchronization optimization algorithm which improves the accuracy of one-way network delay measurement is deduced based on the optimizing goal.
该文根据优化目标推导了时钟同步优化算法，从而提高单向网络时延测量的精确性。
A strategy of fitting offset to adjust time is proposed to conquer the impact of network delay and jitter on clock synchronization effectively.
该文提出采用拟合偏差方法进行时钟调整的策略，以有效克服网络延迟和抖动对时钟同步的影响。
This is a generated clock millisecond delay resulting procedures.
这是一个产生产生毫秒级时钟延时的程序。
As for the high precision positioning of underwater targets, the GPS sonobuoy technique has two bottlenecks: high precision system clock synchronization and high accuracy time delay estimation.
为了实现水下载体高精度的定位，GPS声纳浮标需解决两个方面的技术难点：高精度的系统时钟同步和定位信号的高精度时延估计。
The timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on.
计时器可以履行功能，如频率测量，事务计数，间隔测量，时钟产生器，延迟时候等。
A one-way delay test method for fiber channel network is proposed, named global clock Ethernet synchronization test.
对已有分段聚类算法进行改进，使用软件方法对单向时延序列进行分析，在线检测时钟调整位置。
The delay circuit is used for both frequency and phase adjustments of the output clock.
延迟电路可通用于输出时钟的频率调整以及相位调整这两方面。
Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.
采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。
I often get up at 7, but this morning when I waked up, the short hand of the clock pointed to 6, it's so weird. Actually from today, daylight saving time is ending, the time delay 1 hour than before.
平时我是7点起床，但是今天当我醒来的时候，表的短针才指在6点，这是怎么回事?原来日光节约时间（就是中国以前也用过的夏令时）今天结束，妈妈昨天晚上已经把家里所有的表都调后了一个小时。
I often get up at 7, but this morning when I waked up, the short hand of the clock pointed to 6, it's so weird. Actually from today, daylight saving time is ending, the time delay 1 hour than before.
平时我是7点起床，但是今天当我醒来的时候，表的短针才指在6点，这是怎么回事?原来日光节约时间（就是中国以前也用过的夏令时）今天结束，妈妈昨天晚上已经把家里所有的表都调后了一个小时。
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