Many clock circuits also work with a resistor and capacitor as low-cost timing components or can be driven from an external source.
许多时钟电路也与电阻器和电容器一起使用作为低成本的时间组分或驱动外部输入。
The article discusses the design method of chip clock circuits, power circuits and complex Spaces circuit for the basic hardware of TMS320C5402 and gives the wiring plans.
讨论了TMS320C 5402芯片的时钟电路、电源电路、复位电路等基本硬件电路的设计方法，并给出了接线图。
Devadas has demonstrated that small circuits connected to the cores can calculate the allotment of bandwidth and switch the direction of the connections in a single clock cycle.
Devadas已经成功演示了一种能计算带宽分配且能在一个时钟周期内改变连接传输方向的小型电路。
In design of pulsed asynchronous sequential circuits, it will solve for equations of clock and equations of state, on a symbolic Karnaugh map.
在异步时序电路设计中，它将时钟方程和状态方程的求解归在统一的符号卡诺图上进行。
Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive-applied technique.
固定频率源可以在在通讯系统和雷达系统中作为本机振荡器，也可以作为数字电路的基准时钟信号，因此得到了广泛的应用。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
时钟树的设计是同步数字集成电路设计中的一个重要部分，对系统的性能和可靠性有很大影响。
The three controlling circuits with fast and low clock in code speed adjust technique are designed.
设计了正码速调整技术中快慢时钟的三种控制电路。
According to different sensitive transitions of flip-flops used in sequential circuits, design and analysis methods for asynchronous sequential circuits are proposed by using the combinatorial clock.
本文根据电路中采用的触发器的不同敏感沿，提出采用组合时钟的异步时序电路的设计和分析方法。
This paper concentrates on using gated-clock in low-power design of CMOS circuits.
阐述了如何运用门控时钟来进行CMOS电路的低功耗设计。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
This paper introduces the process of logic design of digital circuits, and mainly explains the function of asynchronous counter and decoder. The digital clock is an example of this application.
本文介绍了数字电路系统的逻辑设计过程，并且着重阐明异步计数器和译码器的功能，数字钟是这方面应用的一个实例。
The design of asynchronous circuits is widely used in modern VLSI design, which is able to resolve the problems of power dissipation, system speed, clock skew, etc.
异步电路的设计能够解决功耗、系统速度、时钟偏移等问题，成为当前VLSI研究的热点。
In the first course of testing, the operating time of compare circuit is brought into play, synchronously, digital signal processor clock all the testing circuits operating time and keep these .
在每次测试第一次通电过程中，控制动作时间比较电路启动，同时数字信号处理芯片自动记录每一路的热敏电阻的动作时间数据，并进行处理。
The paper designs the circuits of working clock and power driver for CCD.
解决了CCD的时序电路及功率驱动电路设计问题。
These functions are realized by the circuits of power, clock, memory, ultrasonic pulse signal occurs and handle, temperature gathered and serial communication in system.
这些功能的实现是通过系统中电控部分的电源、时钟、存储、超声波脉冲信号发生、处理、温度采集、串行通信电路实现的。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The counter is the most commonly used one of the sequential circuits, they not only can be used to count on pulse, still can separate frequency, timing, produce beats pulse and other clock signal etc.
计数器是最常用的时序电路之一，他们不只可以用来指望脉冲，还可以分频，定时，发生跳动的脉搏和其他的时钟信号等。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
Methods and computer readable media for performing scan-based testing of circuits using one or more test clock control structures are disclosed.
公开了使用一个或多个测试时钟控制结构的来执行基于扫描测试的方法和计算机可读介质。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
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