AGI could, its advocates say, work for us around the clock, and drawing on all available data, could suggest solutions to many problems.
那些拥护通用人工智能的人说，它可以全天候为我们工作，利用所有可用的数据，为许多问题提出解决方案。
A real-time clock circuit(X1228)is applied to be an hourmeter, data memorizer and alarm in speedometer.
实时时钟电路（X1228）被用作里程表，数据存储器和车速表中的警报。
In addition to a typically recorded transaction, many innocuous objects, such as parking lots, buildings, and street corners, are instrumented and record large volumes of data around the clock.
除了通常记录的交易之外，许多不活动的事物也被全天不间断地记录下来，比如停车场、建筑物和街道角落，这样数据量就会变得非常大。
The Data and Clock lines are both open collector.
数据和时钟线都是集电极开路的。
The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.
预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟信号进行控制，从而为器件与微处理器或DSP轻松接口创造了条件。
And, the system can realize functions of automatic irrigation, drainage warning, real time clock, historical data inquiry, data up-transmission and two-way communication.
系统能够实现自动化灌溉，具有排水警示、实时时钟、历史数据查询、数据上传及双向通信等功能。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse.
在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。
Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device.
一些设备有两个时钟，一个用于“捕获”或者“显示”数据，另一个则用于提供将数据输入器件的时序。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
In binary synchronous communication, the use of clock pulses to control synchronization of data and control characters.
在二进制位同步通信中，使用时钟脉冲来控制数据和控制字符的同步。
Simulation of relative delays between Data and Clock pulse trains in 0.1 microseconds increments to 3.1 microseconds.
对于数据和时钟脉冲列之间的相关延迟的模拟，以0.1微秒为递增单位增加到3.1微秒。
The host changes the data line only when the Clock line is low, and data is read by the device when Clock is high.
只有当时钟线为低的时候，主机才可以改变数据线(也就是将数据写入到数据线)。数据将在时钟为高电平的时候被设备读龋。
In order to accomplish the data process and conversion, the clock generation circuit, 100% modulation signal and 10% signal demodulation circuit are designed.
为了完成数据的处理和交换，分别设计了时钟产生电路、100%调制信号和10%调制信号的解调电路。
The main system chips used EP1K100QC208-3, make up of the clock module, control module, time module, data decoding module, display and broadcast module.
系统主芯片采用EP1K100 QC 208 - 3，由时钟模块、控制模块、计时模块、数据译码模块、显示以及报时模块组成。
The synchronization and separation of the data and clock from floppy disk driver are one of phase-lock techniques' use in computer field.
对软磁盘的数据和时钟的同步和分离，只是锁相技术在计算机领域的应用之一。
The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟进行控制，从而为器件与微处理器或DSP接口创造了条件。
The battery is used for data back-up in the event of a power failure as mentioned above, and continuous operation of a real time clock.
这个电池的作用是，在发生电源故障前，进行实时数据备份和连续操作。
And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.
论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。
The protocol realized some functions, such as two-way data buffer, shift register, clock circuit and parity check.
在通信协议中，主要实现了双向数据缓冲器、数据移位寄存器、时钟控制电路以及奇偶校验等功能。
It can work either in dynamic or in static state and it also has the functions such as parameter setting, clock setting, data real time displaying, saving, accessing, up sending etc.
实现了动态测量和静态测量，具有参数设置，时钟设置，数据实时处理、显示、存储、查询以及上传等功能。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
It emphasized the programming thoughts of data collection, display, storage, clock control and RS485 communication in software design.
着重阐述了软件设计中数据采集、显示、存储、时钟控制、RS485通信的编程思路。
For substation layer, a feasible strategy for bad data grading handling and a practicable method to establish the uniform clock for the power network were put forward.
对于厂站层，论文提出了对不良数据分级处理和建立全网统一时钟的策略和方法。
It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。
The communication protocol could solve the issue of identifying the data boundaries and the phase error caused by the accumulated error of clock.
协议能有效解决数据边界识别问题和时钟累积误差造成的相位偏差问题。
Overflow and underflow are averted by storing received data in a FIFO at different addresses using a receive address pointer incremented at a receive clock rate.
溢和下溢是通过存储在避免使用一个接收地址指针在接收时钟速度递增不同的地址在接收到的数据的FIFO。
The a data is latched if le is low and clock is held at a high or low logic level.
在一个数据锁存如果LE是低，时钟是在高或低的逻辑电平举行。
Based on real time clock of GPS system, and by means of absolute time-marker, real time data acquisition between different sites was performed in the form of wireless.
以GPS系统实时时钟为基础，通过对绝对时标加以处理，以无线方式实现了不同站点之间的实时数据采集。
Based on real time clock of GPS system, and by means of absolute time-marker, real time data acquisition between different sites was performed in the form of wireless.
以GPS系统实时时钟为基础，通过对绝对时标加以处理，以无线方式实现了不同站点之间的实时数据采集。
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