The invention can be used to increase chip verification efficiency and precision.
采用本发明提高了芯片验证效率和验证精度。
This paper introduces a method of rapid and accurate system on a chip verification.
介绍了一种快速准确的片上系统验证方法。
Chip verification, especially functional verification has become one of the most difficult and challenging issues in IC design.
芯片验证，尤其是功能验证已成为当前集成电路设计中最困难、最具挑战的课题之一。
The paper focus on the following two parts: Logically implementing the AES algorithm of GPON and relative research on the GPON chip verification.
本文所论述的内容主要集中于以下两方面：GPON中AES算法的硬件实现及GPON芯片验证的相关研究。
Adopting this methodology, it can not only verify the correctness of the chip and reduce the possibility of the errors in the chip, but also shorten the co-verification time.
采用这种方法，不仅可以验证处理器芯片设计的正确性，减少错误存在的可能性，而且缩短了芯片验证的时间。
Under pressure of the increase of chip scale and the decrease of timing to market, verification has become the bottleneck of digital IC design.
在芯片规模指数式上升和要求面市时间快速缩短的双重压力下，验证已成为数字集成电路设计的瓶颈。
With the gradual increase of pressure from market, the efficiency of design verification has become one of hot points in the chip design area.
随着市场压力逐渐增大，设计验证的效率已经成为芯片设计领域中关注的焦点之一。
With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。
The third chapter gives proper means of getting valid chip: sufficient verification in design phase and full test in manufacture phase.
第三章的主要内容是保证芯片的正确性的主要方法：要在设计阶段进行充分验证，在制造阶段进行充分测试。
For chip design, verification must be an important part of the design process from the beginning, along with synthesis, system software and debug strategies.
从设计开始到设计综合、系统软件和调试等阶段，验证是贯穿芯片设计全流程的重要组成部分。
With the continuing increase in chip scale and design gates, verification has become the main bottleneck in chip development.
芯片规模不断增加、设计门数不断增长，验证已成为芯片开发的主要瓶颈。
Verification and logic synthesis result show that the DDC chip can meet the requirement, also have stable performance.
验证和逻辑综合结果表明DDC芯片能满足设计要求，性能稳定。
Design circuit for SoC (System on Chip) design verification in FPGA prototype phase and product phase.
设计电路用于片上系统的设计验证，包括FPGA原型阶段和产品阶段。
How to choose an appropriate method of IP core verification has been the primary issue for many chip design corporations.
选择一种合适的验证技术对于很多芯片设计公司而言已经成为了首要问题。
He was an IC verification engineer in Sondrel and responsible for the functional verification of the mixed-signal chip which can be used for electronic compass products from January 2013.
2013年1月至今，在英盛德微电子从事芯片验证工作，完成应用于电子指南针等产品的磁场定位数模混合芯片的研发工作。
Specially, it summarized the lesson which from practice, can help the verification engineers getting to the aim to reduce the chip cost and shorten the time of market.
文中经验教训的总结可以有效地帮助验证工程师达到降低芯片开发成本，缩短面市时间的目的。
Furthermore, it discussed the important parts of the verification process in detail and summarized a whole flow of FPGA verification which will apply to the verification project of the actual chip.
此后又结合实践，详尽叙述了验证中的一些重要环节，并总结出了一套比较完善的FPGA验证流程，可以有效地支撑实际芯片的验证工作。
With Godson-1 processor as the research prototype, a verification method of processors on-chip-debugging function based on JTAG is presented in this paper.
以龙芯1号处理器为研究对象，探讨了基于JTAG的处理器在片调试功能的验证方法。
The functional coverage model was set up based on on-chip-debugging structure features and the virtual verification prototype was built steadily according to the different memory access modes.
根据在片调试的结构特征建立了功能覆盖率模型，并以访存模式为基准分步建立虚拟验证原型。
Experimental result shows that the verification process of yield analysis chip is right and stable.
实验结果证明，成品率分析芯片验证流程具有正确性和稳定性。
The successfully completed of this multi-million gate ASIC, is not only the evidence to the FPGA verification theoretics, but also has a creative significance on other chip.
本文对于百万门级专用集成电路的成功实践，不仅是对FPGA验证理论的证实，而且从验证的思路和方法上对后续芯片有一定的指导意义。
With the support of advanced EDA tools and chip level verification environment, in this paper, the code coverage analysis and statistic job for NSR module are also done.
本文还通过先进的EDA工具及芯片仿真环境的支持，对去噪模块代码覆盖率进行了统计分析。
With the support of advanced EDA tools and chip level verification environment, in this paper, the code coverage analysis and statistic job for NSR module are also done.
本文还通过先进的EDA工具及芯片仿真环境的支持，对去噪模块代码覆盖率进行了统计分析。
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