Due to the latency difference between main memory and on-chip memory cache, POWER7 was designed with three levels of on-chip cache (see Figure 1).
由于主内存和芯片级内存缓存之间的延迟差别，POWER 7设计了三种级别的芯片级缓存机制(见图1)。
The data flow scheme of the MPEG-4 video compression is optimized by utilizing the DSP's on-chip memory.
针对DSP片内资源特点设计了片内存储器数据分配方案，并根据该方案优化了MPEG 4视频压缩的数据流模式。
In this paper, an allocation strategy for on-chip memory is proposed to optimize energy of memory system.
提出一种基于能耗热点的片上存储器静态分配策略。
Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。
The author issues a method of statically initializing task control blocks, and a method of sharing on-chip memory dynamically, in order to save the insufficient resource on micro-controllers.
作者提出了一种任务控制块静态初始化的方法，和一种动态分配片内存储空间的方法，来解决单片机资源紧张的问题。
Remember that a CPU's cache is local (on-chip) memory that offers fast access over the system's memory.
记住CPU缓存是一个本地(片上)内存，提供了比系统内存更快的访问能力。
Remember that a CPU's cache is local (on-chip) memory that offers fast access over the system's memory.
记住CPU缓存是一个本地(片上)内存，提供了比系统内存更快的访问能力。
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