This paper focuses on performance estimation of the embedded microprocessor based on the on-chip bus, including on-chip bus modeling, high-level simulation environment building and their combination.
本论文的主要工作即着重于系统芯片中片上总线结构的性能评价研究，包括总线结构的建模、系统仿真环境的建立以及性能评价的方法。
This paper focuses on performance estimation of the embedded microprocessor based on the on-chip bus, including on-chip bus modeling, high-level simulation environment building and their combination.
本论文的主要工作即着重于系统芯片中片上总线结构的性能评价研究，包括总线结构的建模、系统仿真环境的建立以及性能评价的方法。
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