Key challenges on CMOS scaling down into nanometer regime are discussed, such as power supply and threshold voltage, short-channel effect, quantum effect, random doping distribution and wire delay.
本论文着重论述未来CMOS进入纳米尺寸的关键挑战，如：电源电压和阈值电压减小、短沟效应、量子效应、杂质数起伏以及互连线延迟等影响。
The effect factors such as the buried channel junction depth and substrate doping concentration on the CCD's optimum operating point and maximum charge capacity are analysed.
分析计算了埋沟结深、衬底掺杂等对CCD最佳工作点及最大电荷处理量的影响。
The effect factors such as the buried channel junction depth and substrate doping concentration on the CCD's optimum operating point and maximum charge capacity are analysed.
分析计算了埋沟结深、衬底掺杂等对CCD最佳工作点及最大电荷处理量的影响。
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