The Version 6 mixed release cell administration logic USES this information to determine which administrative functions are appropriate and valid for a given resource on a particular node.
混合了版本单元管理逻辑的版本6使用这些信息来决定在特定节点的给定资源上，哪个管理功能是合适和有效的。
A new DNA-based logic circuit can sense the signs of cancer, compute that a cell is cancerous, and then cause it to self-destruct, researchers say.
研究人员表示，一种新型的基于DNA的逻辑电路能够感知癌症的征兆，发现已经癌变的细胞，然后促使它自动消亡。
False Alarm Rate (CFAR) detector (FUCAP) based on Fuzzy logic, Unbiased Minimum-Variance Estimation (UMVE) and Cell Averaging (CA) is presented in this paper.
基于模糊逻辑，无偏最小方差估计(UMVE)和单元平均(CA)提出一种新的恒虚警检测器(FUCAP)。
Meanwhile, the dynamic logic manufacturing cell concept is adopted to implement the dynamic alliance of virtual enterprise and the reconfiguration of this MES.
同时，采用了动态逻辑制造单元来实现虚拟企业间的动态联盟以及敏捷化智能MES 的可重构性。
This paper presents a fuzzy logic deduction method for quantitative prediction of regional ore resources based on the concept of "cell cluster" and supported by GIS.
论述了GIS支持下的一种基于“单元簇”概念和模糊逻辑推理的多元地学信息综合分析方法及其在区域矿产预测中的应用。
The decomposition of multilevel logic functions based on standard cell libraries used in ASIC synthesis is presented in the paper.
本文提出在ASIC综合技术中基于标准单元库的多级逻辑函数分解技术。
Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
低速单元采用带有电平恢复的传输管逻辑实现，高速单元采用动态传输门逻辑实现。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
此门阵列采用的BFL预功能级标准逻辑单元，具有九种组合逻辑功能及两种不同选择的驱动能力，并具有输出电平调节功能。
By producing evaluating completion signal early and using DSDCVS logic to design computation circuit of reconfigurable cell, a modified control circuit is proposed.
通过提前产生求值完成信号，使用DSDCVS逻辑实现可重构单元的运算电路，改进了异步可重构单元的控制电路。
LUT-based logic cell has very simple routing demands, which is efficient for logic implementation.
基于LUT的逻辑单元有相当简单的布线需求，对于逻辑实现是最为有效的。
The purpose of cell-library binding is to implement the logic functions of a group of Boolean networks by using some library cells.
它的目标是通过特定的方法，把一组布尔网络表述的逻辑功能用具体的库单元实现。
Each cell contains a register. Each register successively acquires logic calculation results in synchronization with a clock and maintains them.
在各单元中包括寄存器，各寄存器与时钟脉冲同步，依次取得逻辑运算结果并加以保存。
It can be applied to extract logic parameters for circuit cell and establish logic parameter library.
该工具可应用于单个电路的逻辑参数的提取，也可应用于逻辑参数库的建立。
Standard logic cells, memory design and IO cell design.
标准逻辑单元，存储电路设计及输入输出单元设计。
The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results.
比较逻辑比较存储单元的阈值电压与至少一对分数参考电压，以生成比较结果。
Because a cell property's value can be an MDX expression, you can perform conditional logic to determine whether the font will be Roman or boldface.
由于一个MDX只能设置一个单元格属性，所以只能通过条件逻辑判断是显示罗马字体还是黑体。
The cell fusion instrument consists of high frequency generator, high amplitude pulse generator and sequence control logic unit.
电致融合仪主要由高频交流场、高压窄脉冲发生器以及控制逻辑单元组成。
The architecture and logical design of ingress process module, which includes receive control FSM, send control FSM and cell position adjustment logic;
通信协议转换逻辑上行方向的系统分析及体系结构设计，包括上行接收状态机、发送状态机、信元内字节位置调整机制等的设计；
The architecture and logical design of ingress process module, which includes receive control FSM, send control FSM and cell position adjustment logic;
通信协议转换逻辑上行方向的系统分析及体系结构设计，包括上行接收状态机、发送状态机、信元内字节位置调整机制等的设计；
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