In CAVLC architecture, we improve the longer scan period of the previous architecture. Also we utilize simple logic operations to compute the address of coding and reduce the coding period .
而在基于上下文之可变长度编码架构上，我们改善了先前架构过长的扫描周期，采用简单的逻辑运算，运算出需编码的位置，使得编码周期大大的缩短。
In CAVLC architecture, we improve the longer scan period of the previous architecture. Also we utilize simple logic operations to compute the address of coding and reduce the coding period .
而在基于上下文之可变长度编码架构上，我们改善了先前架构过长的扫描周期，采用简单的逻辑运算，运算出需编码的位置，使得编码周期大大的缩短。
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