Partial read usually is equal to cache line size in cache manager.
部分读取通常等于高速缓存管理器线尺寸。
In particular, 32-bit and 64-bit operations that don't cross cache line boundaries are atomic.
特别的，32位机和64位机的操作系统没有交叉缓存线的都是回写式的。
Once the cache line is loaded, further reads are much faster and extra RAM accesses are avoided.
一旦缓存线负载，进一步的读入数据会更快并且多余的只读存储存取会被避免。
Future access to num_proc1 by the parent thread results in the reading in of the data from the cache line.
将来父线程对num_proc1的存取会导致从该高速缓存线路的数据读入。
Later, when it becomes necessary to post the modified line to the bus, the whole cache line is written at once.
接着，当需要将修改的线传输给总线时，所有的缓存线会立刻被写入。
A cache line is said to be valid when it contains cached data or instructions, and invalid when it does not.
当一个缓存行中包含有有效的缓存数据或指令时这个缓存行就是有效的，反之是无效的。
If a program reads a single byte in memory, the processor loads the whole cache line that contains that byte into the L2 and L1 caches.
如果一个程序在存储中读到一个单独的字节，处理器就会释放包含字节的所有的缓存线到L2和L1缓存中。
In particular, note that the array is padded out to 16 bytes; this is the size of a cache line, and the DMA engine likes to work in cache lines.
具体来说，请注意数组被补全为16字节；这是缓存线路的大小，dma引擎喜欢按照缓存线路大小进行操作。
If the data or instruction is not present in the cache, or if the cache line is invalidated, the CPU updates its cache by reading the data from the main memory.
如果数据或指令没有出现在高速缓存中，或者如果高速缓存线路无效的时候，CPU通过从主存储器中读数据来更新它的高速缓存。
By separating the two elements of the structure into two different cache lines, modification of one cache line does not cause another cache line to be read in again from the memory.
通过把该数据结构的两个元素分离到两条不同的高速缓存线路，一条高速缓存线路的修改就不会导致再次从存储器读入另外一条高速缓存线路。
Inline assembly is also sometimes needed when you have to, for instance, ensure that a particular set of instructions are in the same cache line, or otherwise mess around with memory maps.
内联汇编有时也是必须的，举例来说，当您需要确保特定指令集都在相同的缓存线上(否则就会浪费内存映像)时。
When the corresponding L2 high-speed cache line in the L2 high-speed cache is confirmed to be modified, the new data is directly written into the corresponding L2 high-speed cache line.
以及当确定所述l 2高速缓存中相应的L2高速缓存线被修改时，直接将新数据写入该相应的L2高速缓存线。
The profiling table provides the percentage and number of samples collected for specified processor events such as the number of cache line misses, Transition Lookaside Buffer (TLB) misses, and so on.
评测表提供为特定的处理器事件收集的采样的百分数或数量，比如高速缓存线路故障的数量、传输后备缓存(TLB)故障的数量，等等。
When a program writes to memory, the processor only modifies the line in the cache, but does not update main memory.
当一个程序写入存储，处理器仅仅只会修改缓存线，而不会更新主要的存储内容。
The next line shows us that while 231MB is being used, only 86MB of this is actually being used by applications; the rest is being used for buffers and cache.
下一行告诉我们尽管有 231MB 内存正在使用，但是应用程序只使用了其中的 86MB；缓冲区和高速缓存使用了其余的内存。
Although looking one line higher at the size of the engine in memory (118,812 KB), we aren't working with a lot of memory, Let's keep cache on the table.
虽然在第一行中，针对引擎的大小来对内存做了考虑(118,812KB)，但是，我们没有使用很多内存，我们为表保持缓存。
You can control the maximum size of the cache by using the command line option in Listing 1, but note that this maximum size may be constrained by operating system restrictions on shared memory
可以使用清单1中的命令行选项控制缓存的最大大小，但是请注意，这个最大大小可能受到操作系统共享内存限制的约束
You can see from the last line in Listing 1 that the configuration file specifies the memory cache as a LRUMemoryCache.
从清单1中可以看出，该配置文件将内存缓存指定为一个LRUMemoryCache。
Once we're done, we need to build the propel model and clear the cache. At the command line, in /column/protected/sf_column, execute the following commands
完成后，需要构建propel模型并清除缓存。
Typically, however, applications start out with an interface to the disk, and must be converted to an in-line cache interface.
但是，通常应用程序最开始使用的是到磁盘的接口，必须转换为内联的缓存接口。
Use the -M command line option to set the maximum size of the cache.
使用-M命令行选项来设置高速缓存的最大大小。
Use the -s command line option with ccache to get statistics about the cache performance (see Listing 3).
在ccache中使用- s命令行选项来获得关于高速缓存性能的统计数据(见清单3)。
Alternatively, you can configure a command-line argument for each node agent that will force a DNS cache refresh on a periodic basis. The property is.
此外，您可以为每个节点代理配置一个命令行参数，这将强制定期刷新dns缓存。
When discussing writes, it's beneficial to discuss an in-line cache (Figure 6).
提到写入时，最好考虑内联缓存(in - line cache)(图6)。
In our example, we will cache fragments of the contents (such as images and JSPs) by the Edge component (typically installed on the front-line Web servers).
在我们的例子中，将使用Edge组件(通常安装在前线的Web服务器上)缓存内容(如图片和jsp页面)的片段。
Thus, the basis for making a decision about placing new data into the cache is a called a "Line Allocation Policy".
因此，为使有关放置新数据的决定的依据 到高速缓存是一种所谓的“生产线分配政策”。
Thus, the basis for making a decision about placing new data into the cache is a called a "Line Allocation Policy".
因此，为使有关放置新数据的决定的依据 到高速缓存是一种所谓的“生产线分配政策”。
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