On modern processors, the cost of a cache miss is significant, so if the language and runtime can help your program achieve better data locality, performance will be improved.
在现代的处理器上，缓存遗漏的成本非常显著，所以如果语言和运行时能够帮助程序实现更好的数据位置，就会提高性能。
Pause 20 seconds between requests; you should see an obvious cache miss because this content has expired per its outgoing headers.
在请求之间暂停20秒；您应当会看到明显的缓存丢失，因为根据它的传出报头，此内容已过期。
Worse, a cache miss when allocating an object on the heap has a particularly nasty memory interaction.
更糟的是，在堆上分配对象时，缓存遗漏还有一个特别讨厌的内存交互。
Thus, every cache miss on the server triggered a callback RPC that had to fetch the user's credential (STKT + PAC) in its entirety.
因此，服务器上的每次缓存缺页都会触发一个RPC回调，它会获取整个完整的用户证书(STKT +PAC)。
CCACHE_LOGFILE — If set, tells ccache to record the hit and miss statistics from the cache in this file.
CCACHE_LOGFILE——设置这个选项告诉ccache随机记录该文件在缓存中的统计信息。
Because you have accessed the portlet only once, you had a "cache miss"; therefore, the cache was then filled with the fragment and is ready to serve any future requests.
由于您只访问了一次Portlet，并且已具有一个“缓存未命中率”；因此，已在此时将片段填充到缓存，该缓存可以针对任何将来的请求提供服务。
I-cache miss (Processor cannot get the next instruction from instruction cache).
I - cache失效(处理器无法从指令缓存获取下一个指令)。
Predictive loading is a strategy by which when you load an object (say, upon a cache miss) and then guess which other related objects might also need at the same time and load them as well.
而当您加载一个对象(比如缓存缺失之后)然后推测同时还需要哪些其他相关对象并加载它们时，则需要用到预测性加载策略。
If the data is not in the cache, then you have a cache miss and you have to get the item from disk, at disk speed (tens of milliseconds).
如果缓存中没有数据，那么就是缓存未命中(cache miss)，必须从磁盘中以磁盘速度(几十毫秒)获取项。
The statistics administration page can be very useful for examining the cache hit-to-miss ratios and eviction statistics to fine-tune cache sizes.
统计信息管理页对于分析缓存的hit- to - miss比例以及微调缓存大小的统计数据都非常有用。
The portlet must be coded such that it anticipates a cache miss; that is, it must not rely on the fact that cached information is available.
必须对Portlet进行编码，以使其能够预期缓存未命中；即，不依赖于缓存信息可用这一假设。
If a D-cache miss (the processor fails to find data in the D-cache) occurs, an interrupt is raised so that the corresponding register can record this event by increasing its value.
如果发生D - cache失效(处理器无法在D - cache中找到数据)，那么发出一个中断，让相应的寄存器可以通过增加它的值记录这一事件。
In which hazard does cache miss fall into?
在高速缓存未命中陷入危险源？
In this case, as well as when any handler indicates that the cached response should be ignored for this request, the request is then handled as if it were a cache miss.
在这种情况下，以及当任何处理常式指出应忽略此要求的快取回应时，就会如同快取遗漏一样处理要求。
In this case, as well as when any handler indicates that the cached response should be ignored for this request, the request is then handled as if it were a cache miss.
在这种情况下，以及当任何处理常式指出应忽略此要求的快取回应时，就会如同快取遗漏一样处理要求。
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