In this paper, an ASIC based on PCI Local Bus SpecificationV2.2 is designed, and its function, timing characteristic and design flow are also presented.
研究并设计了符合PCI规范V2.2的接口芯片，着重阐述了它的功能特点、时序特征及其大致设计流程。
The FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing.
根据PCI总线操作时序，提出了从设备接口控制器的有限状态机模型。
Programmable hardware timing was used in design of microsecond synchronizer based on ISA bus, after pulse generated by oscillator was divided frequency, it was sent to 8254 to count.
基于IS A总线的微秒级同步器采用可编程硬件定时，由晶振发出脉冲经分频后送入8254计数。
At last, 1553 bus circuit design has been finished on the basis of studying the basic function and timing of 1553 chip EP-H31580.
最后，在研究EP -H31580 1553总线芯片的基本功能和读写时序的基础上，完成了1553总线模块的硬件设计。
The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。
If the bus incorporates a robust timing margin, small adjustments in the clock timing should produce no errors.
如果总线有充足的时间间隙，时钟时间上很小的调整不会产生错误。
Design of synchronous cycle trig based on internal bus, consensus definition of sensor sampling and actuator timing and precise data transmission model ensured the synchronization performance.
设计了基于内部总线的同步周期触发，定义了一致的传感器、执行器单元执行时序，以及精确光纤链路数据传输模型，确保测控的高同步性。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
An electronic timing system and synchronization control system are designed based on computer control technology and field bus.
本文基于计算机控制技术和现场总线技术设计了一套行列式制瓶的电子配时系统和同步控制系统。
The invention discloses a bus priority signal timing method based on a running schedule with the adoption of a computer program.
本发明公开了采用计算机程序的基于运行时刻表的公交优先信号配时方法。
Once you select the timing source, you have many options for controlling the final bus frequency.
一旦选择了时钟源，可以有多种控制最终总线频率的选择。
The control boards of the electronic timing system and synchronization control system are connected by using CAN bus.
所设计的电子配时系统由上位机、段控板和机控板组成。
The control boards of the electronic timing system and synchronization control system are connected by using CAN bus.
所设计的电子配时系统由上位机、段控板和机控板组成。
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