Later, when it becomes necessary to post the modified line to the bus, the whole cache line is written at once.
接着，当需要将修改的线传输给总线时，所有的缓存线会立刻被写入。
Each pod has its own processors and memory, and is connected to the larger system through a cache-coherent interconnect bus.
每个pod具有自己的处理器和内存，并通过一条高速缓存一致性互连总线(cache - coherent interconnect bus)连接到较大的系统。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
All models have 8 (2x4) MB cache in the second level and system bus OF FSB 1066 MHz.
所有型号有8 (2x4)M B缓存在第二级和系统总线的财经事务局1066兆赫。
All models have 8 (2x4) MB cache in the second level and system bus OF FSB 1066 MHz.
所有型号有8 (2x4)M B缓存在第二级和系统总线的财经事务局1066兆赫。
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