Some problems in logic cluster boundary scan test could not be neglected.
逻辑簇的边界扫描测试存在一些不可忽视的重要问题。
There are some common methods of design for testability, such as boundary scan test and so on.
目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
The automatic testing software which is compatible with BSDL files and EDIF files can complete multiple boundary scan test tasks.
兼容于BSDL和EDIF文件格式的自动测试向量生成软件可实现多种扫描测试功能。
In this paper, the theory and architecture of boundary scan test technology is introduced and researched, then its application is given.
研究了目前较常用的边界扫描测试技术的原理、结构，并给出了边界扫描技术的应用。
This paper Outlines the design of features related to test and then details the Boundary Scan test strategies developed for different MCM.
本文概要论及与测试相关的设计特性，详细讨论了不同MCM的边界扫描测试策略。
In the end, the boundary scan test technology is introduced as the useful complement to functional self-test method, which can improve the fault isolation rate.
最后介绍了边缘扫描测试技术，指出边缘扫描测试技术是功能自测试方法的有益补充，能够有效提高测试的故障隔离率。
With the continual improvement of the chip's integration level and complexity of print circuit board, the application of boundary scan test technology becomes wider and wider in testing ICs.
随着芯片集成度和印刷电路板复杂度的不断提高，边界扫描测试技术在芯片故障检测中的应用越来越广泛。
JTAG Boundary Scan is a new technique for connection test. With the help of JTAG, we can find out all connection faults of a complicated board or system.
JTAG边界扫描机制是用于在线导通测试的新技术，利用JTAG可以在数分钟内查出复杂插件和系统的全部导通故障。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。
We have developed a new On-line Connecting Test System based on JTAG boundary scan for computer plug-unit or system.
在某计算机系统中设计了基于JTAG边界扫描计算机插件或系统在线导通测试系统，这是一个新颖通用的系统。
Fault injection emulation platform based on Joint Test Action Group (JTAG) boundary scan and dynamic partial reconfiguration is proposed.
提出基于JTAG边界扫描技术和动态局部重配置的错误注入模拟平台。
Test results show that the FPGA chip can realize the desired functions of test and programming in accordance with IEEE1149.1 boundary scan standard, and meets the requirement of the design.
该电路可实现测试、编程功能，并符合IEEE1149.1边界扫描标准的规定，测试结果达到设计要求。
Combining boundary scan with functional test, expanded application of boundary scan and larger testing coverage may be realized.
边界扫描技术与功能测试的结合，可以扩展边界扫描技术的应用范围，实现了更高的测试覆盖率。
Based on the research of primary DFT method and the structure characteristic of designed CPU, the article combines the boundary scan and Build-In Self-Test based on BILBO to test.
本文在对目前主要的可测性设计方法进行研究的基础上，根据所设计CPU的结构特点，采用了边界扫描技术和基于BILBO的内建自测试技术结合的可测性设计方案。
As a standard DFT method, IEEE 1149.1 boundary-scan technique (BST) provides measures to complex interconnect test and can well make up the shortcoming of traditional test techniques.
基于IEEE 1149.1标准的边界扫描技术(BST)作为一种标准化的可测性设计方法，弥补了传统测试的缺陷，为复杂的电路互连提供了测试手段。
On the basis of mixed-signal Boundary scan technology, a scheme of mixed-signal Boundary-scan test system is presented and the hardwares are implemented, including the controller and display unit.
基于混合信号边界扫描技术标准，提出混合信号边界扫描控制器的设计方案并实现了其硬件设计，包括边界扫描控制模块、显示驱动模块等。
Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
建立一个统一的芯片测试和芯片诊断调试接口，形成以边界扫描链为主体，全扫描链为补充的芯片测试机制。
Joint test Action Group designed a common chip boundary-scan structure and test access port criterion which is called JTAG standard to support testing on-board chip or logic.
为支持板上芯片或逻辑的测试，联合测试行动小组专门设计和定义了一种通用的芯片边界扫描结构及其测试访问端口规范，称为JTAG标准。
Meanwhile, how to control the boundary scan bus is mentioned in this paper. As in usual, most devices have no JTAG test access ports, the techniques discussed in this paper are valu…
实际应用中，大多数器件没有边界扫描接口，因此本文所介绍的边界扫描技术实现方法对进行数字系统的可测性设计具有一定的参考价值。
Many in-circuit testers now have boundary-scan test capability. With boundary-scan testing, you can test interconnections on PCBs without using a probe on each node.
很多测试设备具有分界扫描的功能，这样，测试人员就可以直接测试印刷电路板上的互连，而没用必要使用探针去测试每一个节点了。
Two test methods, both test on boundary scan and test-by-divider, are described in details, especially focusing on the maximum output frequency, the range of output frequency and the time to lock.
分别给出了边界扫描测试和分频器测试两种测试方案，并对两种方案进行了比较，指出了各自的适用范围。
The paper proposes applying boundary-scan technology which is widely used in the domain of test to the computer hardware experiment to resolve the two crucial problems of configuration and test.
本文提出将测试领域成熟的边界扫描技术应用在实验系统中，解决配置和验证两大关键问题。
Meanwhile the testing of SOC become more difficult and complex, Boundary-Scan-based Built-in-Test technology give a new solution.
与此同时，片上系统的测试问题也随之产生，基于边界扫描的内建自测试技术为片上系统的测试提供了新的解决方案。
Meanwhile the testing of SOC become more difficult and complex, Boundary-Scan-based Built-in-Test technology give a new solution.
与此同时，片上系统的测试问题也随之产生，基于边界扫描的内建自测试技术为片上系统的测试提供了新的解决方案。
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