This rule can be inverted to store a 0 if the run begins with a 0 bit, but the effect is the same as long as both the encoder and the decoder of the inversion list agree on this detail.
如果开始出现的是0 ，那么这个规则需要改变，但效果是一样的，因为编码器和解码器都遵循这一规则。
The input bit rate and the output frame rate of video decoder is fix, so a Rate Buffer is needed to balance this rate difference.
而经解码后显示的侦速率是恒定的，这就要求在解码端有一个缓冲器来实现输入码率与输出码率间的过渡。
The serial structured decoder can decode one bit per cycle. Because the structure of UVLC(Universal Veriable Length Code) is fixed, "first one detector"is designed to decode UVLC.
变字长解码模块的核心是基于桶形移位器的并行解码结构，使用该结构的解码速度比一次一位的串行结构更快。
The method of designing a parameter configurable and multi-bit parallel BCH decoder is studied in this paper.
本文对可配置参数的多位并行bch译码器的设计方法进行了研究。
With a 16-bit internal hardware counter, the decoder is feasible for interfacing encoder and CPU in the development of multi-axis closed-loop movement control system.
解码器内部具有16位硬件计数器，与CPU接口方便，非常适合于多轴闭环运动控制系统的开发。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
An implementation method and the implementation result of HDTV video decoder bit stream distribution circuit are given out in this paper based on the HDTV video stream construction.
文中在介绍高清晰度电视视频码流结构的基础上，提出了高清晰度电视视频解码器中码流分配电路的实现方法，并给出了实现结果。
An implementation method and the implementation result of HDTV video decoder bit stream distribution circuit are given out in this paper based on the HDTV video stream construction.
文中在介绍高清晰度电视视频码流结构的基础上，提出了高清晰度电视视频解码器中码流分配电路的实现方法，并给出了实现结果。
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