From system model selected, the lengths of hypothetical reference digital link and digital section are chosen, then the properties of bit error and jitter are determined.
从选定的模型，决定了假想参考数字通道和数字段的长度，确定了误码性能和抖动特性的指标。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
Simulations show that adaptively modulated bit leaking method can reduce the jitter in pointer adjustment effectively in both the normal mode and the degraded mode of SDH network.
仿真表明，自适应调制泄漏法在网络处于劣化模式和非劣化模式时都可以有效地抑制指针调整抖动。
Secondly, the effects of the jitter of bit-timing on error performances are discussed.
其次，分析了位定时抖动对误码率的影响。
Jitter and misplace of the bit synchronization signal will reduce the anti-interference performances of communication equipment directly, also increase bit error probabaility.
位同步信号本身的抖动、错位会直接降低通信设备的抗干扰性能，使误码率上升，甚至会使传输遭到完全破坏。
Jitter and misplace of the bit synchronization signal will reduce the anti-interference performances of communication equipment directly, also increase bit error probabaility.
位同步信号本身的抖动、错位会直接降低通信设备的抗干扰性能，使误码率上升，甚至会使传输遭到完全破坏。
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