The VHDL simulator, which implements the behavioral semantics of VHDL descriptions, is one of the most basic components of a VHDL-based EDA environment.

VHDL模拟器是基于VHDL的EDA环境的最基本的组成部分，它所实现的是VHDL描述的行为语义。

youdao

The VHDL simulator, which implements the behavioral semantics of VHDL descriptions, is one of the most basic components of a VHDL-based EDA environment.

VHDL模拟器是基于VHDL的EDA环境的最基本的组成部分，它所实现的是VHDL描述的行为语义。

youdao