This IC design system applicable to the standard cell method is an automatic layout system used for designing Application Specific ICs (ASIC).
采用标准单元方法的集成电路设计系统是一个用于专用集成电路(ASIC)设计的自动布图系统。
The decomposition of multilevel logic functions based on standard cell libraries used in ASIC synthesis is presented in the paper.
本文提出在ASIC综合技术中基于标准单元库的多级逻辑函数分解技术。
The modularization of filter logical architecture is especially suitable for layout design of ASIC with standard cell.
过滤器逻辑结构的模块化特别适宜用标准单元法来实现ASIC(专用集成电路)的版图设计。
A new FIFO-based asynchronous wrapper was proposed, which implemented using only standard cell and optimized in a standard digital ASIC flow.
本文采用通用的数字ASIC设计流程，在仅使用已有标准单元的情况下，提出了一种新的基于FIFO的异步包装。
A new FIFO-based asynchronous wrapper was proposed, which implemented using only standard cell and optimized in a standard digital ASIC flow.
本文采用通用的数字ASIC设计流程，在仅使用已有标准单元的情况下，提出了一种新的基于FIFO的异步包装。
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