Optical Parallel Array Logic System?
光学并行阵列逻辑系统OPALS ？
The method of design of ten's carry reversible counter by use of common array logic element GAL is introduced.
介绍用通用阵列逻辑器件GAL设计十进制可逆计数器的方法。
This paper review elementary theory for new logic circuit with ROM memory array, and provide design method for two practical array logic circuit.
本文论述用ROM的存贮阵列构成新颖的组合逻辑电路和时序逻辑电路的基本原理，并给出两个实际的阵列式逻辑电路的设计方法。
This paper presents the principle and the features of a new spatial amplitude encoding pattern method implementing optical parallel array logic gates.
本文给出了执行光学并行阵列逻辑的一种新的空间振幅编码图形法的原理和特性。
A PHP associative array carries the results of the core bank logic.
一个PHP关联数组用来传递核心银行逻辑的结果。
The sample code USES a utility class EtagComputeUtils to generate a byte array representation of an object and to handle the MD 5 digest logic.
下面的例子使用了一个工具类etagcomputeutils来产生对象所对应的字节数组，并处理MD5摘要逻辑。
It can be used to systematically construct state array and sequence diagram, write logic expressions, and draw control circuit diagram based on technical requirements.
介绍了根据工艺要求系统地构成状态表和程序图，写逻辑表达式。画控制线路的具体方法。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
此门阵列采用的BFL预功能级标准逻辑单元，具有九种组合逻辑功能及两种不同选择的驱动能力，并具有输出电平调节功能。
Especially, the system becomes more concise and stable by use of large scale programmable logic device ISPLSI - 1032e gate array.
在硬件、软件上进行了优化设计特别是采用了大规模可编程逻辑器件ISPLSI- 1032E门阵列使该系统更简洁、稳定。
The programmable digital devices implement the logical function by designed internal logic array block while the traditional digital systems do it by designed printed circuit block.
传统的数字系统通过设计线路板实现系统性能，而可编程器件是通过设计芯片内部的互联逻辑来实现系统功能。
For realizing symbolic substitution rules of binary addition. This paper proposes a simple optical logic system which includes only one 2-d array of optical bistable device.
为了实现二进制加法符号替换规律，本文提出了一种简单的光逻辑系统，它仅包括一片二维列阵光学双稳器件。
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data.
数据总线上的输入数据是否写入存储器，取决于此时的DM的输入逻辑。
Programmable logic, in particular field programmable gate array (FPGA) is such a solution.
可编程逻辑，特别是现场可编程门阵列(FPGA)便是这样的解决方案。
The circuit includes a sequential logic drive circuit, a DC bias voltage circuit and a monolithic temperature control circuit for the focal plane array.
其中包括时序逻辑驱动电路、直流偏置电压电路及单芯片焦平面温度控制电路。
The whole design is realized and verified with field programmable logic array (FPGA).
整个设计以现场可编程门阵列（FPGA）进行了功能验证。
逻辑阵列块 LAB?。
逻辑阵列块 LAB?。
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