It adopts a new systolic array architecture, which can improve the speed by increasing the frequency without the size increased.
设计采用的新型心动阵列结构，可以在有效控制芯片面积的前提下，极大地提高运算频率，从而提高运算速度。
A new approach is presented of the eigen-structure subspace algorithms, the problem of ambiguous estimation in the original algorithm is solved and array architecture is optimized.
提出了改进的特征结构子空间算法，采用二维联合估计方法，解决了原算法存在的角度估计模糊问题。
Poor architecture can cause a wide array of quality problems, including fragility, lack of scalability, and resistance to modification.
低质量的构架会引起大范围的质量问题，包括(软件)脆弱，缺乏升级，以及难以修改。
Looking at the IBM SOA reference architecture above here is a sampling of the vast array of IBM products available for each of the aspects of SOA.
检查上述IBMSOA参考架构，这里只简要介绍可用于SOA各个方面的众多ibm产品中的部分产品。
These capacitors form binary weight array in successive approximation architecture.
这些电容在逐次逼近结构中构成二进制权阵列。
The design idea and system architecture of costumed fiber channel adapter was proposed based on field programmable gate array.
基于现场可编程门阵列的定制的光纤通道适配器，提出了其设计思路和系统结构。
The architecture of real time image processing as pipeline structure, massive array and linear array processing, as well as the image understanding system structures, are discussed and compared.
讨论和比较了实时图像处理中的流水线、大阵列处理器及线性阵列处理器结构及实时图像理解的总体结构。
The design method for the efficient time-varying network architecture of the fractional multiple sampling rate converter is presented and its field programmable gate array (FPGA) is implemented.
提出了分数倍抽样率转换器的高效时变网络结构的设计方法，并用现场可编程门阵列(FPGA)实现。
The design idea and system architecture of costumed fiber channel adapter was proposed based on field programmable gate array(FPGA).
基于现场可编程门阵列（FPGA）的定制的光纤通道适配器，提出了其设计思路和系统结构。
In this paper, some major problems, such as RAID architecture, disk array controller, which need to be solved on theory and engineering has been discussed in detail.
本文将对廉价磁盘冗余阵列体系结构、磁盘阵列控制器及实现过程中理论上和工程上需要解决的若干问题进行一些探讨和研究。
In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.
本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。
This paper presents an architecture based-on shift register array, which can be used for the search for the two search pattern simultaneously.
本文提出了一种基于移位寄存器阵列的硬件结构，该结构能够同时适应对这两种模板的搜索。
The present inventive concept can realize a highly dense memory array with 3d cross-point architecture by simplified processes.
本发明可以通过简化的工艺实现具有3d交叉点结构的高密度存储阵列。
This thesis achieves the following three innovative results: 1 the thesis presents a new parallel array 2-d discrete wavelet transform DWT hardware architecture based on lifting schemes.
以下是本文的三个创新性成果：1设计了一种并行阵列式二维离散小波变换DWT提升格式的硬件结构。
The use of a segmented architecture is well known to the person skilled in the art, as is the fact that it is not necessary to sample onto the sub array.
分段架构的使用对本领域内的技术人员是熟知的，事实上其不必采样到子阵列上。
In contemporary architecture practice, proficiency in an ever-widening array of architecture software is becoming increasingly important.
在当代建筑实践中，精通一系列不断发展壮大的建筑软件变得越来越重要。
The fuse array (40) described herein is very compact and USES little semiconductor area because of its crosspoint architecture.
在本申请中描述的熔丝阵列(40)由于其为交叉点体系结构因此非常紧凑，并且使用很少的半导体面积。
In this paper, we discuss a new memory array-interval decoding architecture, which decreases cross talk parasitical rc aroused effectively during the period of read and writing operation.
针对这个问题给出位线“间隔译码”的组织结构，有效地降低了存储器读写时寄生rc所带来的串扰。
In this paper, we discuss a new memory array-interval decoding architecture, which decreases cross talk parasitical rc aroused effectively during the period of read and writing operation.
针对这个问题给出位线“间隔译码”的组织结构，有效地降低了存储器读写时寄生rc所带来的串扰。
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