We propose a novel architecture with error detection and error correction abilities called complementary logic - alternating-complementary logic (CL-ACL) structure.
提出了具有差错检测和校正能力的、延迟较小的互补-交替互补逻辑结构。
We propose a novel architecture with error detection and error correction abilities called complementary logic - alternating-complementary logic (CL-ACL) structure.
提出了具有差错检测和校正能力的、延迟较小的互补-交替互补逻辑结构。
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