• The timing requirements for PE structure and the adder array for adder tree structure to optimize performance of design are studied and used.

    研究了利用PE(处理单元)结构时序约束加法结构加法阵列优化设计性能

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  • In order to deal with the significant digits addition we designed three inputs adder tree, and give a simple performance discuss of this method.

    针对有效数相加问题,本文提出了输入加法设计方法就其性能作了简要的分析。

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  • We also describe the principle and possibilities of the all-optical prefix tree adder.

    描述前缀加法器原理,说明了其实现的可能性

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  • The model can be extended for studying more complex all-optical circuits of enhanced functionality in which the prefix tree adder is the basic building block.

    提出模型扩展用于研究前缀加法器基本构造模块功能强大复杂全光回路

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  • We propose and describe an all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer (TOAD) using a set of optical switches.

    提出一种基于太赫兹光学非对称解复用器前缀法器,在其中使用多个开关。

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  • A 32-bit sparse tree adder with modified carry tree structure is proposed.

    提出改进进位运算的32位稀疏法器

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  • The prefix tree adder is useful in compound adder implementation. It is preferred over the ripple carry adder and the carry lookahead adder.

    法器适用于复合型加法运算,优于脉动进位加法器超前进位加法器。

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  • The prefix tree adder is useful in compound adder implementation. It is preferred over the ripple carry adder and the carry lookahead adder.

    法器适用于复合型加法运算,优于脉动进位加法器超前进位加法器。

    youdao

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