The task of a phase-lock receiver is to reproduce the original signal while removing as much of the noise as possible.
锁相接收机的作用是重建原信号而尽可能地去除噪声。
Digital phase lock loop is a key part of the digital demodulator.
数字锁相环是数字解调器的关键部件。
The general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product.
本论文对取样锁相理论及技术的全面研究，为新产品开发做了一定的预研工作。
This paper gives a detailed analysis of the principle of the phase lock circuit, one of the most important parts of the QF1052B Standard Signal Generator and provides some methods of checking it.
本文详细分析了QF1052B型标准信号发生器锁相环部分的基本组成及其工作原理，并提出了对此部分电路的检测方法。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
It is noted that the minimum mean square error (MMSE) detector often loses phase to lock a desired signal when the desired signal dips into a deep fade.
在实际通信系统中当信号处于深衰落时，最小均方误差(MMSE)检测器经常失去对信号的相位跟踪。
The phase-locked loop frequency synthesizer is a kind of phase lock installment and it is a kind of separate gap frequency code generator with high stability frequency.
锁相环频率合成器是一种相位锁定装置，是一种频率稳定度较高的离散间隔型频率信号发生器。
A systematical analysis of dynamic characteristic of the pulse-synchronous camera control ystem is described, as to make the results help the researches in phase lock speed-stabilizing ystem.
本文对脉冲同步摄影机控制系统的动态特性进行了系统的分析，以便使所得结果对锁相稳速系统等方面的研究有所帮助。
A fast phase-lock feature can also be enabled to give switch times between 11 and 22 ms depending on absolute frequency and step size.
一种快速锁相功能，也可以启用，使11日至22日开关时间取决于绝对频率和步长毫秒。
However, process mismatches and other factors can cause a small phase difference between the phase of RCLK and the phase of FCLK even when PLL 100 is lock mode.
然而，即使PLL 100处于锁定模式，过程失配和其他因素也可能引起RCLK相位和FCLK相位之间小的相位差。
By using a double phase lock in amplifier to measure the AC strain, the measurement error can be decreased to 0.4% of the total measurement range.
如果使用双相位锁相放大器测量交变的被测量，误差将减小到全量程的0.4%以内。
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。
In general, the design of phase-lock loops has been done by a combination of linear analysis, phase plane plots, rule of thumb, and simulation.
锁相环一般采用线性分析，相平面图，近似计算法以及计算机模拟来设计。
The phase lock loop is a feedback control system that makes two telecommunication signals' phase synchronization, suitable to the synchronous trigger circuit of the convertor device.
锁相环路是完成两个电信号相位同步的反馈控制系统，适宜于变流装置的同步触发电路之中。
The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。
This paper discusses the influence of mixer on the phase lock-loop (PLL) circuit of a local oscillator. In mixer, local signal is produced by the PLL circuit.
本文讨论了采用锁相环路作为本振信号的混频器对本振锁相环路的影响。
A method, correlation algorithm, was promoted to detect phase information in lock-in thermography nondestructive testing in order to reduce sample images.
为了减少图像序列采集数量，针对相位法红外热成像检测提出了获取热波信号相位信息的方法，即相关检测算法。
A method, correlation algorithm, was promoted to detect phase information in lock-in thermography nondestructive testing in order to reduce sample images.
为了减少图像序列采集数量，针对相位法红外热成像检测提出了获取热波信号相位信息的方法，即相关检测算法。
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