In this paper, a hardware algorithm for graphics rasterizer on embedded platform is presented.
提出了一种面向嵌入式平台的图形光栅的硬件实现算法。
Though load balancing is not so significant in execution of a MapReduce algorithm, it becomes essential when handling large files for processing and when hardware resources use is critical.
虽然在执行MapReduce算法时负载平衡不够明显，但在进行大文件处理以及硬件资源利用至关重要的时候它是非常必要的。
With the same simple shake-detection algorithm above, a Perl script, and a monitoring policy, administrators will be better able to track the status of their hardware.
使用同一个简单的震动检测算法、一个perl脚本和一种监视策略，管理员将能够更好地跟踪硬件的状态。
This paper introduces a kind of graph anti-aliasing algorithm and its implement by hardware.
本文研究的主要内容是图形的反走样算法及其硬件模型研究。
Compared with the scan line algorithm, it has a simple data structure, no need to maintain and sort lots of tables, simple implementation, and fitting for being implemented by hardware.
该算法和扫描线算法相比，具有数据结构简单，不需要对众多的表格进行维护和排序，实现思想简洁和适合硬化等优点。
This paper proposes a kind of optimized TSS algorithm and its implementation based on candidate groups hardware architecture.
提出一种改进的三步搜索算法，并采用基于候选组处理的硬件结构实现。
The azimuth testing algorithm for a radar target is introduced in this paper, and the design of system hardware and software is presented.
介绍某雷达目标方位自动显示的方位角测试算法、系统的硬件设计和软件设计。
A variable step uniform quantization(VSUQ) sum-product algorithm(SPA) was developed to reduce the hardware complexity of low-density parity-check(LDPC) code decoding.
为降低低密度奇偶检验码译码的硬件实现复杂度，提出了一种可变步长均匀量化“和积”译码算法。
A novel phase detection algorithm that does not need complete period sampling, phase-locked loops or complex electrocircuit hardware was presented in this paper.
本文提出了一种无需整周期采样、无需锁相环和复杂电路硬件的相位检测算法。
Based on mathematic morphology filtering, a real-time detection algorithm for infrared small target and its realizing technology on DSP hardware are proposed.
基于数学形态滤波，提出了一种红外小目标实时检测的算法及其DSP硬件实现技术。
This paper presents the technological process of a bleaching workshop, the PLC system structure, hardware configuration, software application and the temperature control algorithm.
文中介绍了漂白工段的工艺流程、PLC系统结构和硬件配置及软件实现；并详细介绍了漂白中温度的控制算法。
The paper introduced the numerical control system of tool grinding machine operated by a cheap microprocessor, the interpolation algorithm of its plane contours, and related hardware as well.
介绍了廉价的微处理器刀具磨床数控系统，及其产生平面轮廓的插补算法，以及相关硬件。
This design adopts the algorithm of radix-4 and decimation-in-time (DIT) to devise a real-time FFT hardware processor with practicality.
设计采用基4算法设计了一个具有实用价值的FFT实时硬件处理器。
In this paper, after studed some common string matching algorithms and many matching related hardware structures, a hardware oriented multi-pattern exact string matching algorithm has been presented.
本文首先对与字符串匹配有关的常用算法、各类相关的硬件匹配结构进行了深入分析，并提出了一种面向硬件实现的多模式字符串精确匹配算法。
This paper proposes a novel efficient area reduction solution for hardware implementation of the advanced encryption standard (AES) algorithm which works in SSX11-140 secure processor architecture.
给出了在一种安全处理器(SSX11- 140)中有效缩减AES算法硬件实现面积的设计方案。
System achieved video signal input and output for the video codec algorithm development or video processing product design constructed a high-performance hardware platform.
系统实现了视频信号的输入、输出，为视频编解码算法开发或视频处理产品设计构建了一个高性能的硬件平台。
The range-free algorithm does not need additional hardware, and, thus, it is a cost-effective approach for the WSN localization problem.
而无需测距的定位算法不需要额外的硬件条件，是解决定位问题的一个比较经济适用的方法。
In this paper, a new hardware circuit of real time measuring for mine hoist force diagram based on alternating current sampling is proposed. The software algorithm is also given in the paper.
提出了利用交流数字采样法进行矿井提升机力图实时测定的一种新的硬件电路设计及其软件算法。
After the detailed analysis of EBCOT algorithm and pass-parallel coding technique, a dual context window bit-parallel coding method and its architecture for hardware implementation are proposed.
通过研究EBCOT编码原理和通道并行算法的编码过程，提出了双上下文窗口位并行的EBCOT系数位建模方法，详细说明了使用该算法的系数位建模系统的硬件结构。
The device can be used as a demonstration of computer control system as well as an emulation research for both the software and hardware designing and debugging of the control algorithm.
该系统可作为计算机控制系统教学的演示装置，亦可进行系统硬、软件设计、调试及控制算法的仿真研究。
On the basis of analysis for several kinds of nonuniformity correction algorithms, a new scene-based nonuniformity correction algorithm easy to implement in hardware is put forward.
在分析了几种非均匀校正算法特点的基础上，提出了一种易于硬件实现的新算法，并给出了具体的硬件实现方法。
With the development of LDPC algorithm which has a hardware-friendly trend, the VLSI realization of LDPC decoder is becoming ever the focus of researchers.
随着LDPC译码算法领域的研究日趋成熟和越来越易于硬件实现的发展趋势，LDPC译码器的VLSI实现才逐渐成为研究者关注的焦点。
For the sake of offering more effective management of the signals diffusing in the Computer Hardware Imitation Experiments System, a kind of signal diffuse algorithm is presented.
为了更加有效的管理在计算机硬件仿真实验系统中的信号扩散，本文提出了一种信号扩散算法。
At last, a parallel structure based on master-slave hardware system is adopted, and the problem of algorithm distribution is discussed.
最后基于具体图像处理系统硬件拓扑结构研究了算法并行分配的实现。
Its estimation range is large, about of the symbol rate, while the algorithm proposed requires a very low computational load and is very easy to implement with digital hardware.
可估计的载波频差范围是大的，约为符号率的，并且算法所需的计算负载非常低，适合数字硬件实现。
Therefore, improving the key technologies of AMR algorithm and researching to the hardware realization platform have important practical value and a good prospect of application.
所以对AMR算法关键技术的改进及其硬件实现平台的研究，具有重要的理论研究价值和实际应用前景。
And also analysed the theory, software and hardware circuits of system. Using a software algorithm of temperature compensation in practical measurement, the precision degree can arrive 0.1%fs.
分析了系统设计的理论依据和软硬件实现方案，采用温度补偿算法使补偿后的精度等级达到0 1%FS。
This paper introduces a VAD algorithm with average of the magnitude and weighted zero crossing rate, and the algorithm has been implemented by hardware.
介绍了一种平均幅度和加权过零率的VAD算法，并对该算法进行了硬件实现。
To achieve various stylized visual effects non-invasively in real-time graphic applications, we propose a hardware-accelerated algorithm.
提出一种基于硬件加速的算法，在实时图形应用中非侵入式地获得各种风格化渲染特效。
To reach the demands of the real-time covert communication, the hardware implementation of a new kind of the high efficient information hiding algorithm is proposed.
为满足实时隐秘传输的要求，给出了一种实时高嵌入效率信息隐藏算法的硬件实现。
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