Design work has also built a system is very particular about the power divider, it has a lower frequency than traditional units in terms of series inductance values.
系统还内置一个设计做工都非常讲究的功率分频器，它有着相对传统而言更低的低频单元串联电感值。
A high frequency low power divide-by-2 Injection-Locked Frequency Divider is presented.
设计了一个高频低功耗的注入锁定二分频器。
A modulator reduces the quantization error of the frequency divider.
调制器减少该分频器的量化误差。
A programmable divider used in frequency synthesizer of Rb frequency standard is designed, and the improvement of programmable divider is introduced.
对铷频标中的频率合成器内的程序分频器进行了设计，并介绍了改进后的程序分频器。
Applications of decimal Fraction frequency divider in the area such as direct digital frequency synthesis technology and stepper motor drive speed controller a re introduced.
在此基础上，介绍了小数分频器在直接数字频率合成技术和步进电机驱动速度控制中的两种常见应用。
A frequency low power divide - by - 2 Injection - Locked frequency Divider (ILFD) is presented.
设计了一个高频低功耗的注入锁定二分频器。
Finally, a brief introduction to the applications of the very high speed frequency divider is given.
最后简单介绍了超高速分频器的应用情况。
This paper describes a noise analysis method for a phase switching frequency divider.
介绍了一种相位开关型分频器电路的噪声分析方法。
A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider.
提出了一种基于共振隧穿二极管的新型边沿触发d触发器并将之用于构成二进制分频器。
By theory analysis of divider transfer function of magnitude-frequency characteristics and phase-frequency characteristics, a new method equalizing stray capacitance could be conclude.
并且通过对分压器传递函数的相频和幅频特性进行理论分析，提出一种分布电容补偿的方法。
The logic and circuit design of a very high speed ECL programmable frequency divider is described.
介绍一种ECL高速程控分频器的逻辑设计、电路设计及研制结果。
This paper gives out a design of the equal duty ratio arbitrary integer frequency divider based on FPGA.
给出了一种基于FPGA的等占空比任意整数分频电路的设计方法。
Through analyzing its work principle, we find the method to raise the speed: use a novel CMOS dynamic D flip-flop and an improved synchronous frequency divider.
分析了双模前置分频器的工作原理，提出了提高其工作速度的方法，包括给出一种新型高速CMOS动态D触发器的设计以及同步分频器的改进。
Use a binary digital shifter replace the traditional divider in ADPLL, make the structure simple and keeps the loop gain constant when the frequency multiplication factor changes.
采用数字移位器替代传统的除法器，使得电路结构大大简化，而且在很大的倍频系数范围内都保持很好的稳定性。
Project 1 will be focused on the design and SPICE simulation of a high speed frequency divider for phase-locked loop applications.
专题1主要是讨论用于相锁迴路应用的高速分频器设计和SPICE模拟。
Project 1 will be focused on the design and SPICE simulation of a high speed frequency divider for phase-locked loop applications.
专题1主要是讨论用于相锁迴路应用的高速分频器设计和SPICE模拟。
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