电弧：高压切换产生的RFI(射频干扰)可能会干扰高速逻辑电路。
Arcing: The RFI (radio frequency interference) generated by high voltage switching may disrupt high speed logic circuits.
此外，由此产生的射频干扰(RFI)可能会中断系统中的高速逻辑电路。
In addition, the RFI (radio frequency interference) generated may disrupt high speed logic circuits in the system.
由于XM 可使用多个样式表， 所以对高速缓存的逻辑进行了改进。
Since XM uses more style sheets, the caching logic has been improved.
光分组交换由于缺乏高速光逻辑器件、光缓冲存储器等，因此还处于研究阶段。
OPS still is placed in to study the stage because of lacking of the high-speed optical logic device and optical buffer.
本文介绍了一种基于FPGA的USB2.0高速、低成本的虚拟逻辑分析仪的设计原理与实现方法。
This paper introduces the design and realization of a high-speed and low-cost virtual logic analyzer based on FPGA and USB2.0 bus.
概述活套控制系统在高速线材轧制中的作用、控制原理、PLC逻辑控制及活套调节对精轧机和夹送辊、吐丝机之间张力的影响。
A general introduction was made on effect, control principle and PLC logic control of the loop control system in high speed rod rolling.
查找程序方法内的逻辑和ejbLoad() 方法执行实际的大型机调用，但是从更进一步的意义来说，企业bean仅仅充当了数据高速缓存。
The logic within the finder methods and the ejbLoad() methods performed the actual mainframe calls, but from that point onward, the enterprise bean acted simply as a data cache.
因为从逻辑上划分内存缓冲区或高速缓存内存和固件的内存。
Because memory logically divided on buffer or cache memory and firmware memory.
介绍了在地下漏水探测仪中用CPLD实现高速音频数据采集控制及与单片机的接口逻辑设计。
The gathering and controlling of high speed data of audio frequency by CPLD and the logic design of interface are introduced for underground water leakage detecting instrument.
大规模可编程逻辑阵列（CPLD）的快速开发、在系统编程以及高速可靠的特点使得CPLD在数字系统的构建中起到越来越重要的作用。
The feature of rapidly develop, high speed and high reliability of Complex Program Logic Device(CPLD) makes CPLD playing a more and more role in the design of digital system.
同时，逻辑机制的极端复杂性与局限性，所形成的在线分析技术也是无法满足高速信息交换的需求。
Meanwhile, the formed on-line analytical technology could not fulfill the need of high speed information exchange due to the extreme complexity and limitation of the logical system.
介绍了一种新的高速集成逻辑电路。
数据采集部分采用AD 7862芯片，具有高速的数据采集能力，可编程逻辑CPLD的采用，使得系统具有较强的可扩展性。
The part of data acquisition in the control system is introduced mainly, which USES high-speed data acquisition chip AD7862 and CPLD (complex programmable logic device) to make the system extended.
介绍了LED大屏幕扫描电路的设计方法，阐述了可编程逻辑器件在高速数字系统应用中的优点。
The design method of LED big screen scanning circuit is introduced, and the virtues of programmable logic device application on high-speed digital system are presented.
介绍一种ECL高速程控分频器的逻辑设计、电路设计及研制结果。
The logic and circuit design of a very high speed ECL programmable frequency divider is described.
该模块由高速前放电路，数字逻辑电路，强度调制器驱动电路，自动增益控制电路，以及强度调制器组成。
The module is made of high speed amplifier, AGC circuit, digital logical circuit, intensity modulator drive circuit, and intensity modulator.
该仪器以最新的片上系统芯片FPSLIC为核心处理器，以RTX51为嵌入式操作系统，采用大屏幕液晶显示，实现了多路高速数字信号的逻辑分析。
This instrument uses System on Chip FPSLIC as its core processor, RTX51 as embedded systems and large LCD as displaying, which can analyse many channels logic signals.
设计了以FPGA为核心逻辑控制模块的高速数据采集系统。
The high speed data acquisition system based on FPGA, which is the core logic control module of the system is designed.
若在高速电路设计时不考虑其影响，逻辑功能正确的电路在调试时往往会无法正常工作。
If don't regard to its effects in high-speed circuit design, the circuit with correct logic function often does not work while debugging.
对于系统中复杂且高速的逻辑控制及时序设计及其实现的阐述是论文的另一重要部分。
Also, this paper details the complex and high-speed logic control and timing schedule design.
低速单元采用带有电平恢复的传输管逻辑实现，高速单元采用动态传输门逻辑实现。
Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
本文结合工程背景，运用逻辑平衡的思想对高速数字电路的设计及相关问题进行了全面的研究。
This dissertation focuses on the high performance digital circuits design and relative issues, using the concept of logic balance.
利用FPGA完成复杂且高速的逻辑控制及时序设计，将采集的图像根据视频信号原理进行裁剪并存储在SRAM中。
FPGA is used to achieve the complex and high-speed logic control and the design of time sequence, with grabbed digital video signal cut and stored in SRAM, under the principles of the video signal.
文中分析了机群系统中高速通信网卡对PCI接口的要求，采用紧凑设计思想，将网卡的功能逻辑与PCI接口实现在一个FPGA芯片中。
Requirements for high speed network adapter in cluster were analyzed in this thesis. The function logic of the network adapter and PCI interface could be implemented in a single FPGA chip.
该模糊控制器电路不用cpu，全部算法由数字逻辑电路实现，具有运算速度快的特点，适合于需要高速控制的场合。
No CPU is needed for the fuzzy controller circuit. All algorithms are realized for high speed by digital logic circuits.
改进算法简化系统结构，降低逻辑设计复杂度，节约了高速存储器部分硬件资源。
This algorithm simplifies the system architecture as well as reduces the complexity of logical design. Moreover it also reduces the hardware resources of high speed memory.
在此基础上，采用高速数字信号处理器、大规模可编程逻辑门阵列和实时软件进行系统设计，完成了原理样机的研制。
On this basis, the principle prototype is developed with high speed digital signal processor (DSP), the huge reprogrammable logic gate arrays (FPGA) and real-time software.
本产品专门设计用于提供规则电源，主要是为低压ic应用：如高速总线终端和3.3V低电流逻辑电源等供电。
The product is specifically designed to provide well-regulated supply for low voltage IC applications such as high-speed bus termination and low current 3.3v logic supply.
本产品专门设计用于提供规则电源，主要是为低压ic应用：如高速总线终端和3.3V低电流逻辑电源等供电。
The product is specifically designed to provide well-regulated supply for low voltage IC applications such as high-speed bus termination and low current 3.3v logic supply.
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